A Full Load Range ZVS Isolated Three-Level DC/DC Converter with Active Commutation Auxiliary Circuit Suitable for Electric Vehicle Charging Application

Abstract

The isolated three-level DC/DC converter (ITLDC) can be used to charge electric vehicles. During the constant current charging stage, the ITLDC can be designed to realize nature zero voltage switching (ZVS). However, during the constant voltage charging stage, the charging current is small; thus, nature ZVS cannot be realized. This paper presents an active commutation auxiliary circuit (ACAC) for the ITLDC to realize the full load range ZVS. With the proposed ACACs, all the main switches achieve zero-voltage turn-on and quasi zero-voltage turn-off, and the auxiliary switches realize zero current turn-on and zero-voltage turn-off; thus, the efficiency will be high. The auxiliary currents generated by the ACACs are controllable. During the constant current charging stage, the ITLDC realizes nature ZVS and the auxiliary currents are controlled to zero; thus, the ACACs do not result in high current stress or bring in additional losses, and the efficiency will be high. During the constant voltage charging stage, the charging current decreases with charging time and the charging current is too small to realize nature ZVS. Thus, the ITLDC can work with the proposed ACACs and the auxiliary currents can be controlled within a suitable value to realize ZVS. With the proposed ACACs, the ITLDC can realize ZVS during the whole charging process; thus, the efficiency will be high. The structure and operating principle of the ITLDC with ACACs are introduced and the performance of the proposed TLDC is experimentally verified on a 1.5 kW prototype converter.

1. Introduction

With the characteristics of being environmentally friendly and reducing fuel consumption, electric vehicles (EVs) are becoming popular. The chargers of EVs can be categorized into two classes—slow charging and fast charging. The fast chargers are usually installed in highway rest areas and city refueling points [1]. The slow chargers are usually installed in community parking sites or located on-board. Usually, these chargers include an AC/DC converter followed by a second-stage DC/DC converter [2] or one-stage DC/DC converter powered by a high-voltage DC bus [3]. Some AC/DC converters can be used to charge the EVs directly. However, the control is complex [4]. Usually, DC/DC converters are used in chargers and the input voltage of these DC/DC converters is high. To reduce the voltage stress, the DC/DC converter can be implemented by an isolated three-level DC/DC converter (ITLDC) [5,6]. A four-switch ITLDC was proposed in [7], which has the simplest structure. Many research works focusing on the four-switch ITLDC have been conducted to achieve high efficiency and reliability. To ensure the reliability of the ITLDC, the voltages of the input capacitors and the current of switches should be balanced. The pulse wide modulation methods are proposed in [8,9] to achieve perfect voltage balancing results. The periodically swapping modulation strategy is proposed in [10] to achieve balanced switch currents. To achieve high efficiency in an ITLDC, soft switching should be realized. This paper will focus on the zero-voltage switching (ZVS) of the four-switch ITLDC.

There are many research works focusing on the ZVS of the diode clamping ITLDC. For example, in [11,12], the ZVS is realized with a large load range and reduced circulating loss; in [13,14], the ZVZCS methods are proposed, and some switches realize zero-current turn-on and other switches realize zero-voltage turn-on. However, the research works focusing on the ZVS of the four-switch ITLDC are relatively few and these research works are as follows. The ITLDC will achieve natural ZVS with a high output current and the natural ZVS range can be extended by increasing the leakage inductance of the transformer or adding an external inductor in series with the primary winding of the transformer [11]. However, a too large leakage inductance will result in high duty cycle loss and high circulating loss [11,15]. In [16], a combined DC/DC converter is proposed to realize wide load range ZVS, two ITLDCs’ parallel operation and share two switches of the down bridge; thus, the current stress of the down bridge switches will be high. A wide load range ZVZCS ITLDC with two main switches realized ZVS and another two main switches realized zero-current switching (ZCS) in [17]. However, when the ITLDC is implemented with MOSFETs, the switching losses will not be substantially reduced with ZCS, due to the large output capacitance of MOSFETs. In [6], a zero-voltage switching PWM strategy with capacitor current-balancing control is proposed; the ZVS achievement conditions of the upper bridge switches and the down bridge switches are shifted towards each other in every two switching periods; thus, the switching losses caused by the hard switching at the light load situation can be distributed evenly among the four power switches. However, the soft switching range is not extended with this ZVS method. In [18], a ZVS non-isolated bidirectional DC/DC converter with transient current build-up technique is proposed with a small average auxiliary current, which can be used in ITLDC to realize full load range ZVS. However, this ZVS method needs two auxiliary switches for each bridge and the auxiliary switches are turned off under hard switching conditions.

To extend the ZVS range of the ITLDC, a commutation auxiliary circuit (CAC) can be added. A CAC with one inductance and two capacitances is proposed in [19]. The CAC can be used in different ITLDCs, and also in the four-switch ITLDC, as shown in Figure 1a. However, this CAC will not perform well when the ITLDC is used as an EV charger. According to [20,21], the constant-current and constant-voltage charging strategy is used to charge lithium-ion batteries. In the first charging stage, the batteries are charged with a constant current and, then, the charging process will switch to a constant-voltage stage. During the constant-current stage, the duty cycle of the ITLDC will increase with the increase in battery voltage. During the constant-voltage stage, the output current of the ITLDC will decrease with the charging process time. The maximum value of the auxiliary current i_A is i_{A_peak}, which will change with the duty cycle. The maximum value i_{A_peak} can be expressed as (1) [17] and the change in i_{A_peak} with duty cycle is shown in Figure 1b.

$$i_{\mathrm{A}\text{\_}\mathrm{peak}}=\frac{D(1-D)V_{\mathrm{in}}{T}_{\mathrm{s}}}{4L_{\mathrm{A}}}$$

(1)

where D is the duty, T_s is the period, V_in is the input voltage, and L_A is the auxiliary inductor of the CAC.

As shown in Figure 1b, to achieve ZVS at a small duty cycle, the auxiliary inductor L_A should be designed with a small value. However, the auxiliary current will be large when the duty cycle is large. The auxiliary current will result in high conduction losses and high current stress of the main switches. Moreover, during the constant-current charging stage, the output current is large enough to realize ZVS naturally, and then the CAC is unwanted. A controllable CAC is required to generate a controllable commutation auxiliary current, which does not change with the duty cycle and can be controlled to zero when the ITLDC realizes ZVS naturally.

This paper proposes an active commutation auxiliary circuit (ACAC) with controllable commutation auxiliary current, which will realize a full load range ZVS of the ITLDC. The ACACs can be left unused when the ITLDC realizes natural ZVS, which will result in high efficiency. Since the ACACs will not work when the current of the ITLDC is large enough to realize natural ZVS, the ACACs do not increase the current stress of the main switches. The auxiliary switch achieves zero-current turn-on and zero-voltage turn-off and the switching loss of the auxiliary switch is quite small. The structure and operating principle of the ITLDC with ACACs are introduced and the performance of the proposed ITLDC is experimentally verified on a 1.5 kW prototype converter.

2. Proposed Topology and Working Principle

The topology of the proposed ITLDC is shown in Figure 2. The ACAC consists of a small auxiliary inductor L_A, an auxiliary capacitor C_A and an auxiliary switch S_A. Two ACACs are applied to the ITLDC’s upper bridge and down bridge, respectively. The auxiliary capacitor C_A is large enough so that the voltage of C_A remains unchanged in one period. L_r is the leakage inductance of the transformer and C_b is the DC-blocking capacitor, which is large enough to act as a DC voltage source. C₁~C₄ are the equivalent parallel capacitors, which will achieve a quasi-zero-voltage turn-off condition for the main switches. V_S1~V_S4 are the drain source voltages of the main switches S₁~S₄. The main switches S₁, S₂ are driven by a complementary PWM with dead time and S₃, S₄ are also driven by a complementary PWM with dead time. The PWM phases of S₁ and S₃ are shifted by π degrees.

The operating principle and auxiliary current of the upper ACAC are shown in Figure 3 and the operating principle of the down ACAC is the same as the upper one. Before the switch S₂ is turned off, the auxiliary switch S_A1 is turned on, the voltage V_CA1 is applied to L_A1 and the current i_A1 will increase linearly from zero. The auxiliary switch S_A1 is turned on at the zero-current condition. The auxiliary current i_A1 can be expressed as in (2).

$$i_{\mathrm{A}1}(t)=\frac{V_{\mathrm{CA}1}}{L_{\mathrm{A}1}}t$$

(2)

where V_CA1 is the voltage of the auxiliary capacitor C_A1, and L_A1 is the auxiliary inductance.

The current i_A1 will increase linearly until the main switch S₂ is turned off. When S₂ is turned off, the auxiliary current i_A1 increases to i_{A_peak}, which will be used to achieve the ZVS turn-on of S₁. The auxiliary current i_A1 will discharge the equivalent parallel capacitor C₁ and charge C₂. Once the voltage of C₁ decreases to zero, the antiparallel freewheeling diode D₁ is conducted and the zero-voltage turn-on condition of S₁ is ready, as shown in Figure 3a. The energy to realize ZVS is taken from L_A1 and C_A1, which are large enough to maintain the zero-voltage condition throughout the entire dead time. After S₁ is turned on at zero-voltage condition, the current i_A1 will decrease linearly, which can be expressed as (3). The current i_A1 will decrease to negative until S₁ is turned off. When S₁ is turned off, the switch S_A1 is also turned off. The negative current of i_A1 will flow through the antiparallel freewheeling diode D_A1 and the auxiliary switch S_A1 is turned off at zero-voltage condition. The negative current of i_A1 will discharge the equivalent parallel capacitor C₂ and charge C₁. Once the voltage of C₂ decreases to zero, the antiparallel freewheeling diode D₂ is conducted and the zero-voltage turn-on condition of S₂ is ready, as shown in Figure 3b.

$$i_{\mathrm{A}1}(t)=i_{\mathrm{A}\text{\_}\mathrm{peak}}-\frac{V_{\mathrm{in}}-2V_{\mathrm{CA}1}}{2L_{\mathrm{A}}}t$$

(3)

where i_{A_peak} is the peak value of the auxiliary current, 0 < t ≤ DT_s and D is the duty cycle, and T_s is the PWM period.

With the proposed ACACs, all the main switches realized zero-voltage turn-on even at no load condition, and the auxiliary switch realized zero current turn-on and zero-voltage turn-off. The auxiliary current i_A1 is controllable by adjusting the turn-on time of the auxiliary switch S_A, and the auxiliary current i_A1 will be zero if the auxiliary switch S_A1 is not turned on. If the load is heavy enough, the ACACs will not work and the ITLDC achieves natural ZVS. When the load is light, the auxiliary current i_A1 can be controlled to a suitable value to realize ZVS. Then, a full load range ZVS of the ITLDC can be realized; thus, the efficiency will be high. The detailed working process is analyzed as follows. The main theoretical waveforms of the ITLDC with ACACs are shown in Figure 4, and the positive directions of currents and voltages are marked in Figure 2. Since the working principle of the ITLDC has already been described in [7], here, we focus on the realization of ZVS. One switching period is divided into ten time intervals and the equivalent circuits for each time interval are shown in Figure 5. Before the analysis, the following assumptions are made: (1) the output inductor L_o is large enough, and thus the output current i_o can be assumed to be constant; (2) the magnetizing current is negligibly small; (3) the equivalent parallel capacitors have the same value, i.e., C₁ = C₂ = C₃ = C₄ = C_s; (4) the auxiliary inductors have the same value, i.e., L_A1 = L_A2 = L_A. Detailed analysis for each time interval is described as follows.

Interval 1 (Figure 5a, t₀~t₁): During this interval, the auxiliary current i_A1 will decrease from the maximum value i_{A_peak} to −i_{A_peak}, which can be expressed as (3). The current i_S1 flows though the main switch S₁ and the value of i_S1 is equal to (i_Lr − i_A1).

Interval 2 (Figure 5b, t₁~t₂): At t₁, the main switch S₁ is turned off and the auxiliary current i_A1 reaches the peak value −i_{A_peak}. The current i_A1 and i_Lr will charge C₁ and discharge C₂ until the voltage of C₂ reaches zero; thus, the zero-voltage turn-on condition for the switch S₂ is realized. At t₁, the auxiliary switch S_A1 is turned off at zero-voltage condition.

Interval 3 (Figure 5c, t₂~t₃): At t₂, the switch S₂ is turned on at zero-voltage condition and the converter reaches a freewheeling stage. At t₂, the current i_A1 reaches −i_{A_peak}. Since the voltage of V_CA1 is assumed to be constant, the charge variation of the capacitance C_A1 should be zero. The voltage V_CA1 is applied to the auxiliary inductance; thus, the auxiliary current i_A1 increases linearly, which can be expressed as (4). The current i_A1 will reach zero quickly.

$$i_{\mathrm{A}1}(t)=-i_{\mathrm{A}\text{\_}\mathrm{peak}}+\frac{V_{\mathrm{CA}1}}{L_{\mathrm{A}}}t$$

(4)

Interval 4 (Figure 5d, t₃~t₄): The auxiliary switch S_A2 is turned on at zero-current condition and the auxiliary current i_A2 is built up in a short time. The auxiliary current increases from zero; thus, the auxiliary switch S_A2 realizes zero-current turn-on. At t₄, the main switch S₄ is turned off and the current i_A2 reaches the maximum value i_{A_peak}.

Interval 5 (Figure 5e, t₄~t₅): At t₄, the main switch S₄ is turned off, and the current i_A2 and i_Lr will charge C₄ and discharge C₃ until the voltage of C₃ reaches zero; thus, the zero-voltage turn-on condition for the switch S₃ is realized.

Interval 6 (Figure 5f, t₅~t₆): At t₅, the main switch S₃ is turned on at zero-voltage condition. The current i_A2 will decrease until S₃ is turned off. During this interval, current i_A2 will decrease from the maximum value i_{A_peak} to −i_{A_peak}. The power is transferred from the block capacitor C_b to the load.

Interval 7 (Figure 5g, t₆~t₇): At t₆, the main switch S₃ and the auxiliary switch S_A2 are turned off simultaneously and S_A2 is turned off at zero-voltage condition. The current i_A2 and i_Lr will charge C₃ and discharge C₄ until the voltage of C₄ reaches zero; thus, the zero-voltage turn-on condition for the switch S₄ is realized.

Interval 8 (Figure 5h, t₇~t₈): At t₇, the main switch S₄ is turned on at zero-voltage condition and the converter reaches a freewheeling stage. The auxiliary current i_A2 increases linearly and will reach zero quickly.

Interval 9 (Figure 5i, t₈~t₉): At t₈, the auxiliary switch S_A1 is turned on at zero-current condition and the current i_A1 will be built up quickly. At t₉, the main switch S₂ is turned off and the current i_A1 reaches the maximum value i_{A_peak}.

Interval 10 (Figure 5j, t₉~t₁₀): At t₉, the main switch S₂ is turned off and the current i_A1 and i_Lr will discharge C₁ and charge C₂ until the voltage of C₁ reaches zero; thus, the zero-voltage turn-on condition for the switch S₁ is realized. At t₁₀, the main switch S₁ is turned on at zero-voltage condition and a new cycle begins.

With the ACACs, all the main switches achieved zero-voltage turn-on. Considering that the equivalent parallel capacitors C₁~C₄ limit the rising slope of the voltages across the main switches, the main switches are turned off at quasi zero-voltage condition. The auxiliary switches realized zero-current turn-on and zero-voltage turn-off. The auxiliary current is controllable by adjusting the turn-on time of the auxiliary switch S_A. As shown in Figure 4, the intervals (t₃~t₄) and (t₈~t₉) are used to build the auxiliary current; these intervals can be marked as t_{A_build}. During the constant-current stage, the charging current is large enough to realize ZVS naturally, the auxiliary switch S_A will not turn-on and the auxiliary circuit does not work. During the constant-voltage stage, the charging current is small, and the auxiliary circuit will work to realize ZVS of the main switches; thus, the full load range ZVS can be realized.

3. Discussion of the Proposed ZVS ITLDC

3.1. Design of the Proposed ACAC

3.1.1. The Auxiliary Current i_{A_peak}

To avoid the shoot-through of the bridges, a proper dead time t_dead between the PWM drivers is needed and the dead time t_dead can be designed according to [22]. The dead time will affect the ZVS operation, as shown in Figure 6a; although the collector-emitter voltage of S₁ reaches zero during the dead time t_dead, the zero-voltage condition will not be maintained till the end of the dead time. When the current i_S1 increases to zero and changes to positive, the equivalent parallel capacitor of S₁ will be charged and V_S1 will increase; then, the zero-voltage condition does not exist. To maintain the zero-voltage condition, the auxiliary current should be large enough. As shown in Figure 6b, with a large auxiliary current, the zero-voltage condition is maintained throughout the dead time interval.

Due to the large auxiliary inductor, the current i_A1 is equal to i_{A_peak} throughout the dead time interval. When the ITLDC works with no load, the peak value of the auxiliary current i_{A_peak} reaches the minimum. The voltage of the equivalent parallel capacitors should be discharged to zero in the dead time interval; thus, the minimum value of i_{A_peak} can be expressed as (5). When the output current is not zero, the auxiliary current i_{A_peak} should be larger than I_o/2n (n is the transformation ratio). When the output current is large enough, the current of the leakage inductance will continue not crossing zero throughout the dead time interval. The voltage applied to the leakage inductance is V_in/2; thus, the critical value of the output current to realize natural ZVS can be expressed as (6). When the converter realizes natural ZVS, the auxiliary circuit does not work, and i_{A_peak} is zero. The minimum value of the auxiliary current’s peak value i_{A_peak} can be designed as in Figure 7.

$$i_{\mathrm{A}\text{\_}\mathrm{peak}\text{\_}\min }=\frac{C_{\mathrm{s}}{V}_{\mathrm{in}}}{t_{\mathrm{dead}}}$$

(5)

where C_s is the equivalent parallel capacitor of the main switch, V_in is the input voltage of the ITLDC, and t_dead is the dead time.

$$\frac{I_{\mathrm{o}\text{\_}\mathrm{naturalZVS}}}{n}=\frac{V_{\mathrm{in}}}{2L_{\mathrm{r}}}{t}_{\mathrm{dead}}$$

(6)

where L_r is the leakage inductance of the transformer, and n is the transformation ratio.

3.1.2. The Auxiliary Inductor L_A

When the auxiliary current i_A is positive, the capacitor C_A is discharged, and when the current i_A is negative, the capacitor C_A is discharged. When the ITLDC reaches steady state, the voltage of C_A remains unchanged during one period. Thus, the charge variation of C_A in one period should be zero. According to Figure 4, during the time interval t₀~t₁, the auxiliary current i_A1 decreases from i_{A_peak} to −i_{A_peak}, the voltage (V_CA − V_in/2) is applied to the auxiliary inductance L_A1 and the time is DT_S; thus, the voltage of the auxiliary capacitor C_A can be expressed as (7).

According to Figure 4, in the time interval t₈~t₉, the auxiliary current is built up. The voltage V_CA is applied to the auxiliary inductance L_A1. At t9, the auxiliary current reaches the peak value i_{A_peak}; thus, the time to build up the auxiliary current can be expressed as (8). According to (7), the voltage V_CA changes with the duty cycle and the minimum voltage of V_CA will occur at the minimum duty cycle D_min. The maximum value of the time t_{A_build} should be smaller than (1 − D_min)T_s, i.e., t_{A_build} < (1 − D_min)T_s. Considering that t_{A_build} can be expressed as (8) and the voltage V_CA can be expressed as (7), the maximum value of the auxiliary inductor L_A can be calculated as (9). Large L_A will result in large conduction losses and large ripple voltage of the auxiliary capacitor C_A; thus, the auxiliary inductor L_A can be selected with a small value but much greater than the leakage inductance L_r.

$$V_{\mathrm{CA}}=\frac{1}{2}{V}_{\mathrm{in}}-\frac{2i_{\mathrm{A}\text{\_}\mathrm{peak}}{L}_{\mathrm{A}}}{D{T}_{\mathrm{s}}}$$

(7)

$$t_{\mathrm{A}\text{\_}\mathrm{build}}=\frac{L_{\mathrm{A}}{i}_{\mathrm{A}\text{\_}\mathrm{peak}}}{V_{\mathrm{CA}}}$$

(8)

$$L_{\mathrm{A}}<\frac{D_{\min }(1-D_{\min })V_{\mathrm{in}}{T}_{\mathrm{s}}}{2(2-D_{\min })i_{\mathrm{A}\text{\_}\mathrm{peak}}}$$

(9)

3.1.3. The Auxiliary Capacitor C_A

When the auxiliary current i_A is positive, the auxiliary capacitor C_A is discharged. According to Figure 4, the time when the auxiliary current is positive is (t_{A_build} + DT_s/2) and the peak value of the auxiliary current is i_{A_peak}. As the auxiliary current is triangular, the charge variation during the discharge process can be calculated as (10). The charge variation will cause a voltage drop and the voltage drop can be calculated as ΔQ/C_A. The maximum voltage drop will occur at D_max and D_max is equal to 0.5. If the maximum ripple of the voltage V_CA is set to 5%, (11) can be obtained. Considering that ΔQ can be expressed as (10) and V_CA can be expressed as (7), the minimum value of the auxiliary capacitor C_A can be calculated as in (12).

$$\Delta Q=\frac{1}{2}(t_{\mathrm{A}\text{\_}\mathrm{build}}+\frac{D{T}_{\mathrm{s}}}{2})i_{\mathrm{A}\text{\_}\mathrm{peak}}=\frac{1}{2}(\frac{L_{\mathrm{A}}{i}_{\mathrm{A}\text{\_}\mathrm{peak}}}{V_{\mathrm{CA}}}+\frac{D{T}_{\mathrm{s}}}{2})i_{\mathrm{A}\text{\_}\mathrm{peak}}$$

(10)

$$\Delta V_{\mathrm{CA}}=\frac{\Delta Q(D_{\max })}{C_{\mathrm{A}}}<5\%V_{\mathrm{CA}}(D_{\max })$$

(11)

$$C_{\mathrm{A}}>\frac{\Delta Q(D_{\max })}{5\%V_{\mathrm{CA}}(D_{\max })}=\frac{{(D_{\max }{T}_{\mathrm{s}})}^3{V}_{\mathrm{in}}{i}_{\mathrm{A}\text{\_}\mathrm{peak}}}{0.1{(D_{\max }{T}_{\mathrm{s}}{V}_{\mathrm{in}}-4L_{\mathrm{A}}{i}_{\mathrm{A}\text{\_}\mathrm{peak}})}^2}$$

(12)

3.2. Voltage and Current Stress Analysis

The circuit of the proposed ACAC does not operate in a resonance mode, the voltage of the auxiliary capacitor C_A is stable and the current of auxiliary inductor L_A is controllable. Thus, the proposed ACAC added to the ITLDC will not result in additional voltage stress. The voltage stress of the main switches S₁~S₄ is equal to V_in/2 and the voltage stress of the auxiliary switches is equal to V_CA. When the output current is large enough to realize natural ZVS, the auxiliary circuit does not work; thus, the ACACs do not increase the current stress of the main switches in the ITLDC. The current stress of the main switches is equal to I_oN/n, where I_oN is the designed maximum output current. The current stress of the auxiliary switches is equal to I_{o_naturalZVS}/2n, which can be calculated from (6).

The voltage and current stress of the main switches do not increase with the proposed ACACs. The voltage and current stress of the auxiliary switches are smaller than the stress of the main switches.

3.3. Design of Snubber Capacitor

The snubber capacitor C_s will reduce the dv/dt and the turn-off losses of switches. According to [23], the minimum value of C_s can be expressed as (13), where I_oN is the rated current, and t_f is the turn-off fall time of the switches. To ensure the zero-voltage turn-off condition, the authors suggest that the snubber capacitor is designed slightly greater than the minimum value C_smin, 1.5 C_smin~2 C_smin, for example.

$$C_{\mathrm{s}}>\frac{I_{\mathrm{oN}}{t}_f}{n{V}_{\mathrm{in}}}=C_{\mathrm{smin}}$$

(13)

3.4. Loss Analysis

The proposed ACACs will result in power losses, including the core loss of the auxiliary inductance, conduction losses and switching losses of the auxiliary switch. With the ACACs the main switches realize zero-voltage turn-on and quasi-zero-voltage turn-off. Thus, the switching losses are reduced. The added losses and reduced losses will also be discussed.

3.4.1. The Losses Reduced by the ACAC

The turn-on and turn-off losses of the main switches are reduced. The turn-on losses can be expressed as (14), which consist of the loss caused by the output current and the loss caused by the equivalent output parallel with the main switches.

$$P_{\mathrm{SW}\text{\_}\mathrm{on}}=(\frac{V_{\mathrm{DS}}{I}_{\mathrm{o}}}{n}\frac{t_{\mathrm{r}}+t_{\mathrm{fu}}}{2}+\frac{1}{2}{C}_{\mathrm{s}}{V}_{\mathrm{DS}}^2)f_{\mathrm{s}}$$

(14)

where V_DS is the drain-source voltage; t_r is the current rise time, which can be found in the datasheet; t_fu is the drain-source voltage fall time, which can be calculated according to [24]; C_s is the equivalent output parallel with the main switch, which consists of the added snubber capacitor and the energy-related effective output capacitance C_{o_er}, which can be found in the datasheet; and f_s is the switching frequency.

The turn-off losses can be expressed as (15), and they are mainly caused by the output current.

$$P_{\mathrm{SW}\text{\_}\mathrm{off}}=\frac{V_{\mathrm{DS}}{I}_{\mathrm{o}}}{n}\frac{t_{\mathrm{f}}+t_{\mathrm{ru}}}{2}{f}_{\mathrm{s}}$$

(15)

where t_f is the current fall time, which can be found in the datasheet; t_ru is the drain-source voltage rise time, which can be calculated according to [25].

3.4.2. The Losses Resulting from the ACAC

The losses resulting from the ACAC include the core losses of the auxiliary inductor, conduction losses and switching losses of the auxiliary switch. According to [25], the core losses can be expressed as (16). Since the auxiliary current build-up time is very short, the conduction losses during the auxiliary current build-up process can be neglected; thus, the conduction loss is mainly generated during the DT_s interval, which can be calculated as (17). Since the auxiliary switch realizes zero-current turn-on and zero-voltage turn-off, the switching loss of the auxiliary switch can be expressed as (18).

$$P_{\mathrm{core}}=\mathrm{a}{B}_{\mathrm{pk}}^{\mathrm{b}}{f}^{\mathrm{c}}\times V$$

(16)

where the constants a, b and c are determined from curve fitting, which can be obtained from the datasheet of the core. V is the volume of the magnetic core. B_pk is defined as half the AC flux swing, which can be calculated from the BH curve.

$$P_{\mathrm{Conduction}}=I_{\mathrm{RMS}}^2{R}_{\mathrm{ESR}}=\frac{1}{3}D{i}_{\mathrm{A}\text{\_}\mathrm{peak}}^2{R}_{\mathrm{ESR}}$$

(17)

where I_RMS is the RMS value of the auxiliary current; R_L,ESR is the equivalent series resistance of the auxiliary inductor and drain source on state resistance.

$$P_{\mathrm{SAW}\text{\_}\mathrm{on}}=\frac{1}{2}{C}_{\mathrm{o}\text{\_}\mathrm{er}}{V}_{\mathrm{DS}}^2{f}_{\mathrm{s}}=\frac{1}{2}{C}_{\mathrm{o}\text{\_}\mathrm{er}}{V}_{\mathrm{CA}}{}^2{f}_{\mathrm{s}}$$

(18)

4. Experimental Results

To verify the proposed ZVS ITLDC, a 1.5 kW prototype ITLDC with ACACs is utilized with the specifications shown in

Table 1. The specifications of the prototype ITLDC.

Items	Value
Input voltage Vin	400 V
Output voltage Vout	150 V
Maximum output current Io	10 A
Main switches	IPW65R041CFD
Auxiliary switches	IXFH22N65X2
Diode DR1, DR2	DSEI60-06A
Switching frequency f	40 kHz
Transformer ratio n	1:1
Magnetizing inductances Lm	1.22 mH
DC-blocking capacitor Cb	40 μF
Leakage inductance Lr	1.8 μH
Added snubber capacitor	1000 pF
Dead time tdead	0.35 μs
Filter inductance Lo	0.5 mH
Auxiliary inductor LA	18 μH
Auxiliary capacitor CA	9.4 μF

. When the proposed ITLDC is used to charge EVs, the ACACs mainly play a role in the constant-voltage charging stage. During the constant-voltage charging stage, the charging current changes with charging time and the charging current is relatively small. Then, the ITLDC cannot realize natural ZVS soft switching during the constant-voltage charging stage; thus, the ACACs will work to realize ZVS soft switching. In this experiment, the input voltage is 400 V, which is powered by a programmable DC voltage source. The variable resistor with 80 Ω maximum resistance is used as a load and the output voltage is controlled to 150 V. The snubber capacitors C_s are added in parallel with the main switches, and the equivalent parallel capacitors C₁~C₄ are increased; thus, the main switches are turned off at quasi-zero-voltage condition. A photograph of the experimental platform is shown in Figure 8.

The main waveforms measured are shown in Figure 9, where V_DS1 is the drain-source voltage of the main switch S₁, G_S1 is the drive of S₁, i_o is the output current, i_Lr is the current of the primary winding of the transformer, V_CA1 is the voltage of the auxiliary capacitance C_A1, G_S2 is the drive of S₂, G_SA1 is the drive of S_A1, and i_A1 is the auxiliary current flowing through L_A1. The turn-on process of the main switch S₁ without ACACs is shown in Figure 9a,b. As shown in Figure 9a, the output current i_o is 2 A, and before S₁ is turned on, the voltage V_DS1 is discharged from 200 V to 150 V. As shown in Figure 9b, the output current i_o is 10 A, and before S₁ is turned on, the voltage V_DS1 is discharged from 200 V to 40 V firstly; however, V_DS1 increases to 160 V quickly. In Figure 9a,b, the zero-voltage turn-on condition of the main switch S₁ is unrealized. However, as shown in Figure 9c, the main switch S₁ is turned off at quasi-zero-voltage condition. This is because the equivalent parallel capacitors C₁~C₄ limit the rising slope of the voltage across the main switches. In this experiment, 1000 pF snubber capacitors are added in parallel with the main switches and the time-related effective output capacitance of the main switch is 1485 pF (documented in the data sheet); thus, the snubber capacitors C_s of the main switches are equal to 2485 pF.

In fact, according to (6), to realize natural ZVS, the output current i_o should be larger than 38.9 A. When the output current is not large enough to realize natural ZVS, the proposed ACACs can be used to realize ZVS. As shown in Figure 9d, before S₂ is turned off, the auxiliary switch S_A1 is turned on and the auxiliary current i_A1 increases rapidly from 0 A; thus, the auxiliary switch realizes zero-current turn-on. When S₂ is turned off, the auxiliary current i_A1 reaches the maximum value. The voltage of the auxiliary capacitance C_A1 is steady and the value of V_CA1 is approximately 190 V, which is consistent with the theoretical calculation value. According to (5), to realize zero-voltage turn-on of the main switch, the minimum value of the auxiliary current i_{A_peak_min} should be 2.8 A. According to Figure 7, when the output current is 2 A, the auxiliary current should be larger than 2.8 A; in this experiment, the auxiliary current i_{A_peak} is 3 A. As shown in Figure 9e,f, with the auxiliary current, the main switch realized zero-voltage turn-on. When the output current is 10 A, the auxiliary current should be larger than 5 A; in this experiment, the auxiliary current i_{A_peak} is 6 A. As shown in Figure 9g,h, with the auxiliary current, the main switch realized zero-voltage turn-on. With the proposed ACACs, the main switches of the ITLDC realized zero-voltage turn-on. To verify the efficiency, the efficiency of the ITLDC with the proposed ACACs and without ACACs is measured by a HIOKI power analyzer PW6001 and the efficiency changes with the output power are shown in Figure 10. When the output power is small, the efficiency of the ITLDC with ACACs is slightly higher than that of the ITLDC without ACACs, and when the output power is large, the efficiency of the ITLDC with ACACs is much higher than that of the ITLDC without ACACs.

It is interesting to compare the proposed ZVS method and the state-of-the-art ZVS methods for the four-switch ITLDC. The comparison results are summarized in

Table 2. Comparison of the proposed ZVS method with the state-of-the-art ZVS methods.

Converter	Auxiliary Circuits	Soft Switching of the Switches	Soft Switching Range	Current/Voltage Stress
In [16]	Combined converter	ZVS turn-on and turn-off for all switches	Wide load range	2Io/n, Vin/2
In [17]	Two switches	Q2, Q4 ZVS turn-on and ZCS turn-off, Q1, Q3, Qa1, Qa2 ZCS turn-on and ZVS turn-off	Wide load range	Io/n, slightly higher than Vin/2
In [18]	No auxiliary circuits	ZVS turn-on and turn-off for all switches	Traditional load range	Io/n, Vin/2
In [20]	Two CACs	ZVS turn-on and turn-off for all switches	Wide load range	higher than Io/n, Vin/2
Proposed	Two ACACs	ZVS turn-on and turn-off for all the main switches, ZCS turn-on and ZVS turn-off for the auxiliary switches	Full load range	Io/n, Vin/2

. The auxiliary circuits, soft switching of the switches, soft switching range and current/voltage stress are employed to evaluate the ZVS methods. Each ZVS method has its own advantages. For example, in [16,20], wide load range ZVS turn-on and turn-off for all switches is realized; in [17], wide load range soft switching is realized by the auxiliary circuit with only two switches; in [19], the ZVS is realized with no auxiliary circuits. However, most of them do not realize the full load range ZVS; thus, with the light load situation—for example, the battery floating charge stage—the converter has to work with hard switching. Many ZVS methods realize wide load range ZVS; however, the ZVS range will decrease when considering the dead time between switches. Although two ACACs are added in the proposed ZVS converter, the full load range ZVS of the main switches is realized. Furthermore, the auxiliary switches realized zero current turn-on and zero-voltage turn-off, and this ZVS method does not increase the current stress of the switches.

5. Conclusions

This paper has presented an ACAC for the ITLDC to realize full load range ZVS. With the proposed ACACs, all the main switches achieved zero-voltage turn-on and the auxiliary switches realized zero-current turn-on and zero-voltage turn-off; thus, the efficiency will be high. The auxiliary current generated by the ACAC is controllable, and the ACACs will not work when the current of the ITLDC is large enough to realize natural ZVS; thus, the ACACs do not increase the current stress of the switches in the ITLDC. The ITLDC with the proposed ACACs is suitable for electric vehicle charging applications; during the constant-current charging stage, the ITLDC can be designed to realize nature ZVS; during the constant-voltage charging stage, the charging current will decrease, and the ITLDC can work with ACACs to realize ZVS; thus, high efficiency can be achieved during the whole charging process.