Design and Analysis of a Low-Voltage VCO: Reliability and Variability Performance

Abstract

This paper investigates an adaptive body biasing (ABB) circuit to improve the reliability and variability of a low-voltage inductor–capacitor (LC) voltage-controlled oscillator (VCO). The ABB circuit provides VCO resilience to process variability and reliability variation through the threshold voltage adjustment of VCO’s transistors. Analytical equations considering the body bias effect are derived for the most important relations of the VCO and then the performance is verified using the post-layout simulation results. Under a 0.16% threshold voltage shift, the sensitivity of the normalized phase noise and transconductance of the VCO with the ABB circuit compared to the constant body bias (CBB) decreases by around 8.4 times and 3.1 times, respectively. Also, the sensitivity of the normalized phase noise and transconductance of the proposed VCO under 0.16% mobility variations decreases by around 1.5 times and 1.7 times compared to the CBB, respectively. The robustness of the VCO is also examined using process variation analysis through Monte Carlo and corner case simulations. The post-layout results in the 180 nm CMOS process indicate that the proposed VCO draws a power consumption of only 398 µW from a 0.6 V supply when the VCO frequency is 2.4 GHz. It achieves a phase noise of −123.19 dBc/Hz at a 1 MHz offset and provides a figure of merit (FoM) of −194.82 dBc/Hz.

1. Introduction

Over the past decades, biosensors have become one of the most important analytical devices that serve as an indispensable platform for biotechnology and life science research. Much research focuses on expanding the evolving bio-sensing from off-site laboratory tests to research in the place of patient care or bedside laboratory tests that are referred to as Point-of-Care testing (PoC). The PoC platform enables easy-to-use, rapid diagnosis and a compact size at an affordable price, but these specifications make the construction of such a PoC device quite a challenge [1,2,3,4,5,6]. The major challenge that must be overcome to develop PoC devices is the monolithic integration of biochemical methods (assays) with biosensor arrays. Complementary metal–oxide–semiconductor (CMOS) technology that offers cost efficiency, low power consumption, and a significant degree of design flexibility, as well as being equipped for the monolithic integration of a large number of transistors that provide array implementation for parallel analyte detections, is a promising candidate to develop PoC devices. It is notable that although incorporating CMOS technology in biosensor design has an outstanding and undeniable impact on system performance, challenges remain in designing biosensors. These challenges essentially include the interface design that couples the assay to the integrated chip, which generally requires additional post-fabrication processes to boost compatibility in sensing modalities [7,8,9]. CMOS technology enables the bulky and expensive instrumentation to be effectively integrated into a low-cost chip, and providing an accurate platform to measure physical changes comes from biological activity. CMOS sensors can be classified into various types based on the detection systems such as electro-chemical [10,11,12,13,14], optical [15,16,17,18,19], magnetic [20,21,22,23,24,25,26,27,28,29,30,31], mechanical [32,33], and thermal [34,35,36,37].

One of the wildly used blocks of the CMOS sensor structure is the inductor–capacitor (LC) oscillator, which can be employed in the sensing, receiving, or transmitting part. For instance, the main core of the frequency-shift-based magnetic sensors is realized with the LC oscillator [20,24,28,29,31], and this oscillator works as a sensing element. In this type of sensor, during the detection process of magnetic nanoparticles, the effective inductance of the resonator changes, which subsequently leads to a resonant frequency down-shift of the LC oscillator. It is noteworthy to mention that due to the fact that there is no consideration for robust operation due to the process, voltage, and temperature (PVT) variations, the oscillation frequency is sensitive to environmental perturbations, which can lead to undesired frequency drifts and impacts of the detection sensitivity on the oscillation frequency shift. In order to achieve robust performance, the oscillator should be designed for the worst-case condition that consequently results in high power consumption.

Another example of sensors for the investigation of the critical role of LC oscillators is nuclear magnetic resonance (NMR) sensors. The main building block of an NMR system is a magnet to produce a static magnetic field, a radio-frequency (RF) coil surrounding a sample, and an RF transceiver to generate excitation RF magnetic fields and monitor the resonance [38]. In NMR sensors, the LC oscillator can be utilized in the RF transceiver [21,23]. For instance, in the NMR system that is reported by Dreyer et al. [31], a VCO is utilized in the phase-locked loop (PLL) as a frequency synthesizer for RF implementation of the transceiver. However, the PLL guarantees the robust performance of the VCO, and it consumes lots of power and area.

VCO-based capacitive sensors are often utilized for measuring complex permittivity and conducting dielectric spectroscopy [39,40,41]. In most structures of VCO-based capacitive sensors, the VCO plays the role of sensing by exposing the tank capacitance to the samples. In the design of such sensors, it should be considered that a single VCO is highly sensitive to variations in PVT, so the sensing results can be affected by environmental effects. In order to overcome this issue, a differential technique such as the utilization of two VCOs as a sensing and reference and differentiating their output frequencies can be employed to enhance the performance of the sensors. It is important to note that the two VCOs should be similar for achieving proper operation. So, this technique, besides consuming more power compared to a single VCO, suffers from a mismatch between two VCOs. In the work in [39], presented by Helmy et al., a VCO is employed to detect the dielectric constant of organic chemicals. When the tank capacitance of the VCO is exposed to the liquid, the oscillation frequency shift will be proportional to the dielectric constant of organic chemicals. In this design [39], the VCO is embedded inside a power-hungry block of a PLL to achieve self-sustained operation.

It is noteworthy that the application of VCOs extends well beyond CMOS sensors, playing a critical role in various systems [42,43,44,45,46,47]. For instance, Lee et al. [46] reported an inductively powered scalable 32-channel wireless neural recording system-on-chip (SoC) for neuroscience applications. In this work, the open-loop VCO is employed to upconvert the baseband pulse width modulation (PWM)–time division multiplexer (TDM) signal through frequency-shift keying (FSK) and is then amplified through RF and transmitted through a miniature wideband monopole antenna. As another example, in [42], Abdelhalim et al. proposed a 915 MHz frequency-shift keying/on–off keying (FSK/OOK) wireless neural recording SoC that utilized a VCO embedded in a PLL to generate stable and tunable RF signals essential for wireless communication. In this design, the closed-loop PLL transmitter prevents the VCO frequency from drifting by ensuring the output frequency is locked to a precise reference crystal oscillator, but it suffers from high power consumption.

During recent decades, a low-voltage and low-power design of VCOs has continuously drawn intensive research. To achieve low power consumption, shrinking the device size for low-voltage operation has become a popular solution. Continuous scaling in device dimensions makes sub-micrometer CMOS transistors susceptible to reliability issues such as channel hot-electron degradation, gate dielectric breakdown, and bias temperature instability [48,49,50,51,52]. These effects cause performance degradation in circuits over time, raise the transistor threshold voltage ($V_{th}$), and drop the electron mobility (${\mathrm{\mu }}_n$), which ultimately results in circuit malfunction [53,54,55]. Some approaches have been developed to mitigate the performance challenges of device reliability. Overdesigning is one of the approaches that is used in the design of circuits for consistent reliability performance. However, this approach increases the power dissipation and the chip area. So, it cannot be accepted as a beneficial solution. Recently, many papers have been reported in the literature to reduce the circuit overdesign while increasing its robustness against reliability effects [56,57,58,59,60,61]. For instance, in [59], Yuan et al. proposed an adaptive gate–source biasing circuit to keep the overdrive voltage of a metal–oxide–semiconductor field-effect transistor (MOSFET) constant, and its performance was then verified for the reliability design of a class AB power amplifier. The presented result shows that the use of an adaptive gate–source biasing circuit makes the power-added efficiency of the power amplifier robust against the threshold voltage and mobility variations.

Another approach utilizes a body bias scheme to improve process variability and circuit reliability [60,61]. The reliability analysis of an MOS varactor for a CMOS LC cross-couple VCO is investigated in [62] by Liu. Based on our knowledge, the impact of the variability and reliability of cross-coupled transistors that provide negative impedance is not examined. In the VCO structure, transconductance of the cross-coupled pair transistors reduces when subjected to a threshold voltage shift and electron mobility degradation, which lead to increases in the phase noise and may cause the oscillation to stop [63,64]. The design of the VCO for low-voltage and low-power applications becomes more challenging and the circuit response will be more sensitive to reliability issues. In RF circuits, there has been active research on low-power low-voltage VCOs [65,66,67,68] and each method has its own advantages and disadvantages.

In this work, an adaptive body basing (ABB) circuit is presented for the design of a 0.6 V LC VCO with a reliability that effectively suppresses the threshold voltage shift and the electron mobility degradation. This paper is organized into four subsequent sections. In Section 2, the proposed structure is presented. In the next section, post-layout simulation results using 180 nm CMOS technology are presented. Finally, the post-fabrication practical consideration and conclusions are presented in Section 4 and Section 5, respectively.

2. Circuit Design

2.1. Proposed Low-Voltage VCO Design

A widely known oscillator structure is the cross-coupled VCO, which is shown in Figure 1. The cross-coupled transistors M₁ and M₂ provide an equivalent negative resistance to neutralize the resistive loss in the LC tank circuit.

The design of the VCO based on the tail current source prevents circuit performance variations due to bias, device, and process variations, but results in a higher power dissipation and degraded phase noise due to the flicker noise up-conversion. On the other hand, due to the limited voltage headroom by the tail current source, this VCO will not exhibit the appropriate performance in low-supply-voltage operation.

In this paper, an ABB circuit is used, which, in addition to helping to eliminate the tail current source and low-voltage operation, contributes to the reliability performance of the VCO. Figure 2 shows the proposed VCO that consists of the conventional VCO topology with an ABB circuit. The voltage $V_B$ feeds back from the ABB circuit to the body of VCO transistors, which acts as a controlling signal and changes their threshold voltage for compensating the $V_{th}$ variation effects of VCO transistors. To further understand the behavior of the proposed VCO, let us explain the operation as follows: When the $V_{th}$ of M₁(M₂) increases, the current I_C will decrease and lead to the increase in the voltage $V_B$. As a result, the $V_{th}$of M₁(M₂) will decrease and the compensation process arising from reliability degradation will take place. Also, a similar process for the compensation of electron mobility shift takes place, which is illustrated in the following analytical equations.

2.2. Analytical Equations

The start-up oscillation condition is given by the following equation [69]:

$${|-2/g}_m|\le R_P$$

(1)

where $g_m$ and $R_P$ are the transconductance of transistor M₁(M₂) and the loss of the LC tank, respectively. $g_m$ can be expressed as [70]

$$g_m={\mathrm{\mu }}_n C_{ox} \left(\frac{W}{L} \right)\left(V_{GS}-V_{th}\right)=\beta \left(V_{GS}-V_{th}\right)$$

(2)

Due to the body effect, the $V_{th}$ of M₁(M₂) is well known as [70]

$$V_{th}=V_{th0}+\gamma \left(\sqrt{2{\phi }_f-V_{bs}}-\sqrt{2{\phi }_f}\right)=V_{th0}+\gamma \left(\sqrt{2{\phi }_f-V_B}-\sqrt{2{\phi }_f}\right)$$

(3)

where $V_{th0}$ is the threshold voltage at $V_{bs}$ = 0, $\gamma$ is the body effect coefficient, ${\phi }_f$ is the bulk Fermi potential, and $V_{bs}$ is the voltage between the body and source terminal. According to (3), $V_{th}$ can be varied by changing ${ V}_B$, where an adaptive threshold voltage variation of VCO transistors can be obtained.

Now, inserting (3) in (2) results in the following:

$$g_m=\beta (V_{GS}-V_{th0}-\gamma (\sqrt{2{\phi }_f-V_B}+\sqrt{2{\phi }_f})=g_{m0}-\beta \gamma (\sqrt{2{\phi }_f-V_B}+\sqrt{2{\phi }_f})$$

(4)

Examining Figure 2b, the equation for $V_B$ is given as

$${R_{C}I}_C+V_B=V_{DD}$$

(5)

The DC current across the M_C transistor is expressed as [70]

$$I_C\approx \frac{1}{2} {\mu }_{n}Cox {\left(\frac{W}{L}\right)}_C {(V_{GS}-V_{thC})}^2 \approx \frac{{\beta }_C}{2}{(V_{DD}-V_{thC})}^2$$

(6)

where ${\beta }_C$ and $V_{thC}$ are the MOSFET structure coefficient and threshold voltage of M_C, respectively. Replacing $I_C$ from (6) into (5) gives

$$V_B=V_{DD}-\frac{{\beta }_C}{2}{ R}_C {(V_{DD}-V_{thC})}^2$$

(7)

In (7), the deviation in $V_B$ because of the threshold voltage variation maintains the following relationship:

$$d{V}_B=\raisebox{1ex}{$d{V}_B$}\!\left/ \!\raisebox{-1ex}{$d{V}_{thC}$}\right.d{V}_{thC}={\beta }_C{R}_C\left(V_{DD}-V_{thC}\right) d{V}_{thC}$$

(8)

So, the variations in $g_m$ as a result of the body effect can be obtained as (9).

$$d{g}_m=d{g}_{m0}+\gamma \beta \frac{d{V}_B}{2\sqrt{2{\phi }_f-V_B}}$$

(9)

Now, inserting (8) in (9) results in the following:

$$d{g}_m=d{g}_{m0}+ \frac{d{V}_{thC}}{2\sqrt{2{\phi }_f-V_B}}{ \times \beta \gamma \beta }_C{R}_C\left(V_{DD}-V_{thC}\right)$$

(10)

This relation verifies the compensation effect as the first term displays the transconductance shift in M₁(M₂) due to $V_{th}$ variations, and the compensation effect resulting from the body bias of M₁(M₂) by M_C is realized in the second term of (10). So, the transconductance variation due to the threshold voltage degradation and process variation is reduced. The rate of $d{g}_m$ is dependent on $\gamma$, ${\beta }_C$of the M_C transistor, $\beta$of VCO transistors, and $R_C$, which should be carefully determined to achieve a better design.

The VCO performance is also sensitive to the mobility drift. When the mobility reduces, the transconductance of the VCO thus decreases. The $V_B$ fluctuation resulting from mobility degradation by using $V_{B }$ from (7) can be derived as (11):

$$d{V}_B=\raisebox{1ex}{$d{V}_B$}\!\left/ \!\raisebox{-1ex}{$d{\beta }_C$}\right.d{\beta }_C={-\frac{1}{2} R}_C {(V_{DD}-V_{thC})}^2 d{\beta }_C$$

(11)

The transconductance fluctuation subject to $d\beta$ and $d{V}_B$ is given by (12), each term of which can be expressed as (13) and (14).

$$d{g}_m=\raisebox{1ex}{$d{g}_m$}\!\left/ \!\raisebox{-1ex}{$d\beta $}\right.d\beta +\raisebox{1ex}{$d{g}_m$}\!\left/ \!\raisebox{-1ex}{$d{V}_B$}\right.d{V}_B$$

(12)

$${\raisebox{1ex}{$d{g}_m$}\!\left/ \!\raisebox{-1ex}{$d\beta $}\right.=V}_{GS}-V_{th0}-\gamma (\sqrt{2{\phi }_f-V_B}+\sqrt{2{\phi }_f})$$

(13)

$$\raisebox{1ex}{$d{g}_m$}\!\left/ \!\raisebox{-1ex}{$d{V}_B$}\right.=\gamma \beta \frac{d{V}_B}{2\sqrt{2{\phi }_f-V_B}}$$

(14)

By using (11)–(14), the transconductance variation can be written as (15):

$$g_m={[ V}_{GS}-V_{th0}-\gamma (\sqrt{2{\phi }_f-V_B}+\sqrt{2{\phi }_f}\left)\right] d\beta -\beta \frac{\gamma { R}_C}{4\sqrt{2{\phi }_f-V_B}} {(V_{DD}-V_{thC})}^2 d{\beta }_C$$

(15)

The electron mobility reduction of the VCO transistor decreases the transconductance of M₁(M₂), while the reduction in M_C’s electron mobility increases the $V_B$ voltage, which increases the transconductance of VCO, thus finally maintaining a stable transconductance of M₁(M₂). So, the introduced ABB besides suppressing $V_{th}$ variations can degrade the mobility variation.

Since phase noise is an important issue in VCO design, studying phase noise is important [71,72,73]. The phase noise of an LC oscillator at an offset frequency of Δf from the frequency of oscillation $f_0$ normalized with respect to the carrier is given by [73]:

$$L\left(\mathsf{\Delta }f\right)=10{log}_{10}[\frac{F.K.T}{Q^2}.\frac{R_P}{V_{PP}^2}.( {\frac{f_0}{∆f})}^2]$$

(16)

where F is the noise factor modeling the noise contribution of the active core, K is Boltzmann’s constant, T is the absolute temperature, Q is the tank’s quality factor, $R_P=2\pi f_{0}LQ$ is an equivalent resistor modeling the loss of the LC tank, and $V_{PP }$ is the voltage swing. One of the major contributing factors for phase noise is the $V_{PP}$ or, in other words, the transconductance of a transistor. A larger value of transconductance and, consequently, $V_{PP}$ enhances the quality factor of the resonator, which leads to the improvement in phase noise performance [1]. The ABB technique not only results in increased transconductance and thus improves the phase noise performance, but it also helps to reduce the phase noise variations due to $V_{th}$ and ${\mu }_n$ variations by decreasing the $V_{PP}$ and transconductance drift. The simulation results that validate this issue are given in the following section.

3. Post-Layout Simulation Results

The post-layout simulations of the presented structure are carried out using 180 nm CMOS technology. The dc power consumption of the proposed VCO under 0.6 V of power supply is 398 µW, only 10.9 µW of which is drawn by the ABB circuit. The frequency of the VCO is tunable from 2.379 GHz to 2.461 GHz. Figure 3 shows the phase noise of the VCO for a center frequency of 2.4 GHz. The phase noise at 1 MHz of offset is equal to −123.19 dBc/Hz. It is noteworthy to mention that in order to measure phase noise in practice, a spectrum analyzer [42,74,75] and phase noise meter [76] can be used.

The VCO is simulated with the proposed ABB circuit and constant body bias (CBB). The threshold voltage and the mobility are independently swept to achieve a normalized phase noise, voltage swing, and transconductance plot versus the normalized threshold voltage, and the mobility drifts and results are displayed in Figure 4 and Figure 5, respectively. Figure 4 shows the normalized sensitivity of the VCO versus the normalized threshold voltage variation. Figure 4a illustrates the normalized phase noise sensitivity of the VCO with the ABB circuit and with the CBB for the 16% normalized threshold voltage shift, which are 0.27% and 2.26%, respectively. The normalized sensitivity of the VCO versus normalized threshold voltage variation for the voltage swing and the transconductance in the 16% normalized threshold voltage shift are 4.97% and 14.6%, respectively, with the ABB circuit and 22.6% and 44.9% with the CBB, respectively. So, the sensitivity of the normalized phase noise, voltage swing, and transconductance of the VCO with the proposed ABB circuit decreases by 8.4 times, 4.55 times, and 3.1 times compared to the CBB, respectively. Also, the normalized sensitivity of the VCO versus the normalized mobility variation with the ABB circuit and with the CBB is shown in Figure 5, which illustrates that the sensitivity of the normalized phase noise, voltage swing, and transconductance of the VCO with the proposed ABB circuit decreases by 1.5 times, 1.4 times, and 1.7 times compared to the CBB, respectively.

To study the robustness of the structure against process variation, its performance is investigated through Monte Carlo analysis with a run number of 200 and the results are shown in Figure 6 and Figure 7. From Figure 6, the standard deviation of the VCO with the ABB circuit is observed to be less than 177 m, while, in the case of the CBB, it is around 453.87 m. Also, according to Figure 7, the standard deviation of the voltage swing is 29.45 m and 59.17 m with the ABB circuit and CBB, respectively. The promising results from the threshold voltage variation, mobility shift, and Monte Carlo imply the conclusion that the proposed VCO is able to reduce the reliability issue effects and offer an acceptable insensitivity against process variation. The layout and the dimensions of the VCO with the proposed ABB circuit are shown in Figure 8 in which the occupied area is around 0.567 mm × 0.621 mm, and the ABB circuit uses 36.6 µm × 48 µm of this area. The design parameters of the proposed VCO are summarized in

Table 1. Circuit design parameters.

Parameters	Values	Parameters	Values
WM1/LM1	6 × 2 µm/0.18 µm	L	9.46 nH
WM1/LM1	6 × 2 µm/0.18 µm	RB	20 kΩ
WMC/LMC	1.5 µm/0.18 µm	RC	25 kΩ
C	190 fF

.

To compare the performance of the proposed structure with other VCOs, a figure of merit (FoM) is defined as follows [77]:

$$FoM=L\left(∆f\right)-20\log \left(\frac{f_0}{∆f}\right)+10\log \left(\frac{P_{DC}}{1 \mathrm{m}\mathrm{W}}\right)$$

(17)

where L(Δf) is the phase noise in dBc/Hz at offset frequency Δf from oscillation frequency $f_0$ with a DC power consumption of $P_{DC}$ in mW. The results of the circuit simulation in all process corners are summarized in

Table 2. VCO performance in different corners.

Corners	a SS	b FF	c FS	d SF
Phase Noise (dBc/Hz)	−122.1	−123.18	−123.55	−122.83
FoM (dBc/Hz)	−193.52	−193.37	−193.63	−194.65

^a Slow NMOS Slow PMOS; ^b Fast NMOS Fast PMOS; ^c Fast NMOS Slow PMOS; ^d Slow NMOS Fast PMOS.

. It can be seen that the FoM remains relativity constant in the various design corners, which confirms the robustness performance of the designed VCO. The performance of VCO is compared with some other structures in

Table 3. VCO performance comparisons.

Work	a [65]	b [68]	b [78]	b [79]	b [80]	b This Work
CMOS Process (nm)	180	180	180	180	180	180
Power Supply (V)	1.1	1.8	1	1.2	0.8	0.6
Power consumption (mW)	1.4	1	c 3	1	3.14	0.398
Oscillation Frequency (GHz)	2.4	4	5	5	5.4	2.4
Phase Noise (dBc/Hz) @ 1 MHz	−122.85	−116.8	−108	−117.7	−119.5	−123.19
FoM (dBc/Hz)	−189	−188.9	−177.21	−191.8	−189.18	−194.82

^a Measurement; ^b Simulation; ^c QVCO, half power is taken for evaluation.

, which illustrates, in addition to the advantages in terms of power consumption and phase noise, that the proposed VCO also has a better performance compared to the works in the FoM.

4. Post-Fabrication Practical Consideration

In this manuscript, we present a comprehensive exploration into the design and analysis of a VCO, elucidating the nuanced advantages inherent in optimal reliability and variability performance through meticulous post-layout simulations. Following the fabrication of the CMOS chip, where the proposed VCO seamlessly integrates with a dedicated CMOS sensor, an imperative facet involves the experimental characterization of reliability and variability performance. This entails a judicious manipulation of the body performance, discerning its impact on phase noise results. This empirical examination serves as a litmus test, unequivocally demonstrating the efficacy of the proposed VCO. Furthermore, the replication of this meticulous evaluation across a myriad of fabricated dies assumes paramount importance. This iterative process serves not only to underscore the resilience of the proposed VCO but also to establish a robust benchmark for reliability and variability performances across diverse chip implementations. The VCO serves as a fundamental building block, seamlessly interfacing with output power amplifier blocks tailored to specific applications. Consequently, the VCO can be strategically linked through a buffer, significantly constraining the requisite power demand. As the primary focus of this paper revolves around the VCO’s design and reliability, a detailed analysis of output power and efficiency will be reserved for subsequent stages of the circuitry. It is noteworthy that the examination of output power and efficiency, as observed in other referenced papers, has been notably sparse, often limited to the characterization of the voltage swing of the output voltage.

5. Conclusions

A 0.6 V VCO with a high immunity to threshold voltage variations and electron mobility shift has been proposed. The proposed VCO achieves both low-power consumption and a reliability performance utilizing an ABB circuit. The operational principle of the structure is discussed and its most important relations are derived. The robustness of the structure is examined using the threshold voltage shift, electron mobility decrement, and process variation analysis through Monte Carlo and corner case simulations. Finally, its performance is verified through post-layout simulations in the 180 nm CMOS process. The results show that the sensitivity of the normalized phase noise of the proposed VCO under a 0.16% threshold voltage shift and 0.16% mobility variations decreases by nearly 8.4 times and 1.5 times compared to the CBB, respectively. The VCO has a phase noise of −123.19 dBc/Hz at a 1 MHz offset and provides an FoM of −194.82 dBc/Hz while consuming a low power of 398 µW. The proposed VCO, with its emphasis on low power consumption and exceptional reliability, emerges as a compelling alternative for the design of fully integrated transceivers-on-chip, poised to cater to a diverse range of industrial and medical applications.