Design and Performance Evaluation of a Step-Up DC–DC Converter with Dual Loop Controllers for Two Stages Grid Connected PV Inverter

Abstract

In this work, a non-isolated DC–DC converter is presented that combines a voltage doubler circuit and switch inductor cell with the single ended primary inductor converter to achieve a high voltage gain at a low duty cycle and with reduced component count. The converter utilizes a single switch that makes its control very simple. The voltage stress across the semiconductor components is less than the output voltage, which makes it possible to use the diodes with reduced voltage rating and a switch with low turn-on resistance. In particular, performance principle of the proposed converter along with the steady state analysis such as voltage gain, voltage stress on semiconductor components, and design of inductors and capacitors, etc., are carried out and discussed in detail. Moreover, to regulate a constant voltage at a DC-link capacitor, back propagation algorithm-based adaptive control schemes are designed. These adaptive schemes enhance the system performance by dynamically updating the control law parameters in case of PV intermittency. Furthermore, a proportional resonant controller based on Naslin polynomial method is designed for the current control loop. The method describes a systematic procedure to calculate proportional gain, resonant gain, and all the coefficients for the resonant path. Finally, the proposed system is simulated in MATLAB and Simulink software to validate the analytical and theoretical concepts along with the efficacy of the proposed model.

1. Introduction

In recent years, Photovoltaic (PV) holds a pivotal position in ever-increasing energy demand due to easy accessibility, easy installation, high return on investment, and low maintenance cost [1]. A complete PV system consists of a PV array, DC–DC converter (optional), DC-link (DCL) capacitor, inverter, filter, and a grid. Therefore, based on the devices, the PV system configuration is categorized into two types i.e., single-stage and two-stage configuration systems. A single-stage system consists of a PV array, DCL capacitor, inverter, filter, and a grid. In this system, the weight and size of the system are considerably reduced but complexity is greatly increased due to the handling of different functionalities (Maximum Power Point Tracking (MPPT), current control, voltage control, and grid synchronization) by the inverter alone. Moreover, for some applications, the PV voltage needed to be increased to the desired level that cannot be achieved without the use of a DC–DC converter. Therefore, to reduce the system complexity and widen its applications range, a DC–DC converter is introduced in the two-stage configuration system [2]. A schematic of the 2-stage three-phase (3Φ) grid-connected PV system used in this research work is shown in Figure 1.

In the 1st stage of the PV system, a DC–DC boost converter is used to extract the maximum power from the PV panel through the maximum power point technique and lift-up the voltage level according to the desired application. Generally, the classical converters such as boost, Single Ended Primary Inductor Converter (SEPIC), and cuk, etc. are used to attain a High Voltage Gain (HVG). For this purpose, a converter is needed to be operated at a high duty cycle, which has some disadvantages, such as (a) increased duty cycle causing lower efficiency due to increased losses in parasitic resistances of a diode, capacitor, and inductor; (b) as the duty cycle increases, the voltage stress on the switch increases; and (c) increased conduction and switching losses [3].

To overcome the above-mentioned limitations, numerous researchers have designed different converter topologies that can be categorized into isolated and non-isolated topologies based on coupling [4]. A transformer is used in isolated topologies to attain a HVG; however, due to the heavy weight of the transformer and its core and winding losses, they are not feasible for low power PV applications. Consequently, the authors used non-isolated topologies to overcome the issues in isolated topologies [5,6,7,8,9]. A coupled inductor-based Switch Inductor (SL) configured high lift-up converters for renewable application is proposed in [5]. Due to the usage of coupled inductors, the efficiency of these topologies is low due to the leakage inductances of the windings. The authors proposed single inductor-based converter topologies that can achieve a HVG while maintaining good efficiency [6,7,8,9]. In [6], eight different SL-based converter topologies are presented, in which SL is configured with traditional boost, cuk, and SEPIC. Although HVG is achieved by most of these topologies, usage of high component count increases the operational complexity and cost of the converters. An SL and Switch Capacitor (SC)-based improved cuk converter is presented in [7]. This topology is very attractive in terms of HVG but the utilization of two switches and a high number of magnetizing components causes an increment in the control, complexity, and cost. A single switch SEPIC-based modified converter topology is proposed in [8]. However, even though a high voltage gain is achieved for continuous input current, the converter initially suffers from high conduction losses as voltage stress on the switch is equal to the output voltage. An SL/SC-based cascaded boost converter proposed in [9] can achieve HVG with reduced component count but is unable to attain high efficiency. To overcome the limitations in the above-discussed topologies, in this research work, an SL configured hybrid topology that combines the Voltage Doubler Circuit (VDC) with the SEPIC converter is proposed. The most prominent features include high voltage conversion ratio, fewer components, single switch, low voltage stress on semiconductor components, and contiguous input current.

In the second stage of the PV system, besides DC–AC inversion, the functionality of the inverter also involves grid synchronization, current control and protection, and DCL voltage regulation, etc. Therefore, for the smooth and stable performance of the PV system, the inverter control plays a prominent role and is usually implemented in the form of two cascaded loops i.e., outer Voltage Control Loop (VCL) and inner Current Control Loop (CCL). A VCL is responsible for maintaining a constant DCL voltage and generates a reference for the current loop. A CCL is responsible for grid synchronization and injection of a high-quality current [2]. Generally, a Proportional Integral (PI) controller is implemented in the VCL, however, due to PV intermittency, a PI controller fails to maintain a constant DCL voltage due to its fixed gain parameters [10]. Therefore, to enhance the system performance, an arbitrary real term is introduced in the PI controller through fractional calculus and named the Fractional Order Proportional Integral (FOPI) controller [11]. Although the system performance is improved, high ripple contents and distortion from the reference are observed during uncertainties (PV intermittency). A Sliding Mode Controller (SMC) for DCL regulation in proposed in [12]. This controller has a fast dynamic response but the waveforms suffer from chattering phenomena. To enhance the SMC performance and smoothen the shattering effect, the authors introduced an integral term in the SMC [13]. The performance of the PV system is enhanced to a great extent by using fuzzy PI and fuzzy SMC controllers in [14]. However, these controllers have complex architectures and failed to achieve high-quality waveforms. Due to the above discussed limitations in the DCL controller topologies, there is a need to develop a controller that adopts the system uncertainties and ensures the system stability. Therefore, such a controller is needed to be designed that adopts the system dynamics and regulates a DC-link voltage. Hence, in this research work, a Back Propagation (BP) algorithm-based Adaptive Proportional Integral (API) and Adaptive Fractional Order Proportional Integral (AFOPI) controllers are designed. The parameters of these controllers will be updated automatically, in case of any environmental variation or disturbance, and achieve a regulated voltage at a DC-Link.

To maintain a high-quality grid injected current, PI or Proportional Resonant (PR) controllers are usually applied in the inner current control loop. However, when a PI controller is applied in a stationary frame, it cannot track the sinusoidal reference accurately; therefore, the system variables need to be transformed into a synchronous frame that requires large calculations [15]. On the other hand, a PR controller is highly suitable to track the sinusoidal reference and thus, making it an optimal solution for inverter-based grid-connected PV applications. It provides an infinite gain at the selected resonant frequency (at other frequencies there exists almost no gain), and thus, the zero steady-state error can be easily attained [16]. Although it has a high tracking capability, the output current of the grid connected inverter is not invulnerable for harmonic content that usually occurs due to the non-linearities in converter and inverter. Therefore, to reduce or eliminate the harmonic contents, a selective Resonant Harmonic Compensator (RHC) can be added to a PR controller [16]. The performance of the system is greatly improved by using a PR controller and can be found widely in the literature. However, most of the researchers did not explain the design and tuning procedures of their respective controller in detail, and the trial-and-error method is adopted to find the optimal gain values. Although some of the researchers described the design procedure in a continuous-time domain, most of the Grid Connected PV Inverter (GCPVI) applications involve digital implementation. Therefore, the authors in [17] proposed a digital PR controller that has a simple control architecture and tuning methodology. Compared to the conventional methodology, which involves complex trigonometric equations, this work presents a systematic procedure to calculate proportional gain (k_p), resonant gain (k_ir), and the coefficients of the resonant path. However, it shows an effective performance, although it is limited to 1Φ grid connected system and is developed by considering the dynamic behavior of LC filter. However, most of the grid connected power systems involves 3Φ operation and operates at a low frequency. At low frequency the size of L or LC filters becomes very bulky and expensive as a result LCL filters being introduced. In addition to the cost and size, LCL filter offers numerous other advantages such as: (a) smoothens the inverter output current, (b) low Total Harmonic Distortion (THD), (c) improved performance, and (d) and high attenuation [18]. Due to these advantages, in this research work, a PR controller proposed in [17] is modified by considering the dynamics of LCL filter and implemented in a 3Φ grid connected PV system.

The core contributions of this work are listed as:

• A transformer-less high voltage gain DC–DC converter is presented that extracts the maximum power from the PV panel by using Perturb and Observe (P&O) MPPT technique and step-up the low generated PV voltage to a level applicable for grid connected PV inverter. In the proposed topology, a voltage doubler circuit and switch inductor cell are integrated with the SEPIC converter to attain a high voltage conversion ratio. The prominent features of the converter include single switch, simple control, low voltage stress, high efficiency, and fewer components.
• Back propagation algorithm-based API and AFOPI controllers are designed to regulate a DC-link voltage in case of PV intermittency. This adaptive scheme enhances the system performance and handles the system uncertainties by dynamically updating the control law parameters. The proposed controllers have a faster dynamic response and easy implementation, which improves the system stability.
• Based on the Naslin polynomial method, a PR controller is designed, considering the dynamic behavior of an LCL filter. In the proposed controller, no parameter is computed empirically or by trial-and-error method. To show the effectiveness of the controller, it is implemented in a 3Φ grid-connected PV system that results in low THD.

The rest of the manuscript is divided into the following sections as: A schematic and detailed analysis of the first stage of the PV configuration system, including MPPT algorithm and DC–DC converter, which are elaborated on in Section 2, while the second stage that involves DC-link voltage and current controllers are discussed in Section 3. The performance validation of the proposed system is described in Section 4. Finally, this research work is concluded in Section 5.

2. Analysis of DC–DC Converter

Due to the dependency of the Maximum Power Point (MPP) of the PV array on climatic parameters, the position of MPP varies indefinitely. Therefore, to precisely locate the MPP, numerous MPPT algorithms were reported in literature, that vary from each other in various aspects such as complexity, cost, type of sensors required, implementation, and range of effectiveness [19]. In this research, a P&O technique is adopted due to its simplicity and easy implementation, as presented in Figure 2a [19]. According to the operating voltage and current, the P&O technique generates a Pulse Width Modulation (PWM) for the converter as shown in Figure 2b. Generally, the PV system generates a low-level voltage that is needed for amplifying the appropriate operation of the inverter; therefore, a step-up converter is designed, which is discussed below. Moreover, the specifications of the PV panel and the gain parameters of the PI controller used to drive the converter switch are listed in

Table A1. PV panel specifications at (1000 kW/m², 25 °C).

Parameter	Symbol	Value
Voltage at MPP	VMPP	29.9 V
Current at MPP	IMPP	7.65 A
Nominal power	PMPP	228 W
Open circuit voltage	UOC	37.1 V
Short circuit current	ISC	8.18 A

and

Table A2. Controllers Gains.

Controller	Parameter	Value
Controller of Boost Converter
PI	kp	0.01
	ki	0.5
DC-Link Voltage Controller
PI	kp	32
	ki	210
FOPI	kp	17
	ki	105
	λ	0.715
API	kp	8
	ki	23
	γ	400
AFOPI	kp	18
	ki	145
	λ	0.545
	γ	230
Current Controller
PR	Kp	7.074702865475842
	Ki	5.716971169217982
	a0	1
	a1	−1.999990433144820
	a2	0.999990575266452
	b0	9.424777960769379 × 10−6
	b1	−9.424777291035913 × 10−6
	b2	0
	C	4.441300946117881 × 10−5

, respectively.

2.1. Proposed Converter Topology and Operating Modes

A schematic circuitry of a single switch high lift-up DC–DC converter is presented in Figure 3. It consists of an input voltage source (U_PV), switch (S), diodes (D₁, D₂, D₃, D₄, D₅, and D₆), inductors (L₁, L₂, and L₃), and capacitors (C₁, C₂, and C_DC). In this converter, the VDC and SEPIC converter are arranged in such a manner that it enhances the voltage conversion ratio. Furthermore, the primary inductor of the SEPIC converter is replaced with the SL unit (L₁, L₂, D₁, D₂, and D₃) to further enhance the voltage conversion characteristics. The inductors L₁ and L₂ of SL unit have the same magnitude and are always connected to the input source, therefore, the converter input current will always be continuous in nature.

The proposed converter can operate in two operating modes, i.e., Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). The CCM can be divided into two switching intervals, while a DCM can be divided into three switching intervals. A detailed analysis of CCM and DCM are discussed below in detail. However, for simplicity, the following considerations are made in theoretical analysis: (a) the Equivalent Series Resistances (ESRs) value of all components used in converter are not taken into account during the analysis of operating modes, (b) the capacitors are large enough so that they act as a constant voltage source, (c) the leakage inductances have a low value and are not considered in analysis.

2.1.1. Continuous Conduction Mode

Based on the switch characteristics of the converter, its operation is discussed for two switching intervals, i.e., (t₀ ~ t₁) (S is ON) and (t₁ ~ t₂) (S is OFF). The equivalent circuitries of both switching intervals along with the direction of current flow (red arrows) are presented in Figure 4a,b respectively, whereas its typical waveforms in steady state are sketched in Figure 4c.

• Switching Interval (t₀ ~ t₁)

In this switching interval, switch (S) is turned and diodes (D₁, D₃, and D₅) are in forward conduction mode, while the diodes (D₂, D₄, and D₆) are in reverse biased state as presented in Figure 4a. The inductors (L₁ and L₂) will be charged from input source (U_PV) through D₁ and D₃. As L₁ and L₂ have the same magnitude, the same amount of current will therefore be flowing through them and is charged in parallel (i.e., U_L = U_L1 = U_L2, and i_L = i_L1 + i_L2). The inductor (L₃) is also charge in this interval and U_C1 − U_C2 is applied to it. Moreover, C₂ discharges to charge C₁ and L₃. The capacitor C_DC also discharges, and its stored energy is used to feed the load.

• Switching Interval (t₁ ~ t₂)

During this interval, diodes (D₁, D₃, and D₅) and switch (S) are turned OFF, while the diodes (D₂, D₄, and D₆) are in forward conduction mode as presented in Figure 4b. As D₁ and D₃ are in reverse biased and D₂ is in forward biased, L₁ and L₂ therefore act as a series connected circuit (i.e., i_L1 = i_L2). The stored energy in L₁ and L₂ are used to charge C₂ through D₄ and also transfer its energy to support the load through C₁ and D₆. L₃ also discharges in this interval to charge C_DC and support the load.

2.1.2. Discontinuous Conduction Mode

Based on the switch characteristics, the operation of the converter in DCM is divided in three switching intervals, i.e., (t₀ ~ t₁) (S is ON), (t₁ ~ t₂) (S is OFF), and (t₁ ~ t₂) (S is OFF). The typical waveforms of proposed converter in steady state operating in DCM are presented in Figure 5a.

• Switching Interval (t₀ ~ t₁)

In this switching interval, switch (S) and diodes (D₁, D₃, and D₅) are in forward conduction mode while all other diodes are in reverse biased as shown in Figure 4a. The inductors (L₁, and L₂) stores energy by using input voltage source while U_C1 − U_C2 is applied across L₃. This mode ends when the current flows through switch S and diodes (D₁, D₃, and D₅) becomes zero at t₁.

• Switching Interval (t₁ ~ t₂)

In this interval, the diodes (D₂, D₄, and D₆) are in forward biased while all other semiconductor components are in reverse conduction mode as shown in Figure 4b. The inductors discharges in this interval to charge the capacitors and supports the load. This mode ends when the current flowing through diodes (D₂, D₄, and D₆) becomes zero.

• Switching Interval (t₂ ~ t₃)

During this interval, switch (S) remains in turned OFF state and all the diodes (D₁, D₂, D₃, D₄, D₅, and D₆) are in reverse conduction mode as presented in Figure 5b. The voltage that appears across inductors (L₁, L₂, and L₃) becomes zero and the current flowing through inductors is continued as constant. During this mode, the load is supported by the output or DC-link capacitor (C_DC). This mode ends when the switch (S) is turned ON and returns to the first operating mode.

2.2. Performance Evaluation of Converter

In this section, different characteristics such as voltage stress, voltage gain, design of inductors and capacitors, and loss analysis of the proposed converter in CCM mode are discussed. Moreover, a comparative analysis of proposed topology with other topologies is also presented.

2.2.1. Voltage Gain Derivation

The output voltage (U_O) of the converter is given as,

$$U_O=U_{C1}+U_{C2}$$

(1)

as it is assumed that the converter is operating in a CCM and therefore that the average inductor voltage at steady state condition is zero. Therefore, by applying inductor volt-second balance theorem over one switching cycle to L (L₁ = L₂ = L) we produce,

$${\displaystyle \underset{0}{\overset{Ts}{\int }}{U}_L(t)dt=(U_{PV})\left(D{T}_S\right)}+\left(\frac{U_{PV}-U_{C2}}{2}\right)\left(\left(1-D\right)Ts\right)$$

(2)

where D is the duty cycle of the switch. By solving (2), we produce the capacitor voltage (U_C2) as,

$$U_L=0\Rightarrow U_{C2}=\frac{1+D}{1-D}{U}_{PV}$$

(3)

Similarly, by applying inductor volt-second balance theorem to L₃ over one switching cycle we produce,

$${\displaystyle \underset{0}{\overset{Ts}{\int }}{U}_{L3}(t)dt=\left(U_{C1}-U_{C2}\right)\left(D{T}_S\right)}+\left(U_O-U_{C2}\right)\left(\left(1-D\right)Ts\right)$$

(4)

Solve Equation (4) for U_C1 we produce,

$$U_{L3}=0\Rightarrow U_{C1}=\frac{D}{1+D}{U}_O$$

(5)

Put (3) and (5) in (1) and rearrange them, we produce a voltage gain of the proposed converter in CCM as,

$$\frac{U_O}{U_{PV}}=\frac{{\left(1+D\right)}^2}{1-D}$$

(6)

2.2.2. Voltage Stress Calculation

The voltage stress on the semiconductor components can be calculated as,

$$U_S=U_{D4}=U_{D6}=\frac{1+D}{1-D}{U}_{PV}$$

(7)

$$U_{D1}=U_{D3}=\frac{D}{1-D}{U}_{PV}$$

(8)

$$U_{D2}=U_{PV}$$

(9)

$$U_{D5}=U_O-U_{C2}$$

(10)

From (7), it can be observed that the proposed topology exhibits lower voltage stress compared to the classical converters, thus results in lower conduction losses.

2.2.3. Design of Inductors and Capacitors

The design of inductors is based on the value of current ripples (Δi_L), and is considered between 5–10% of the nominal output current to achieve optimal inductor size [20]. Therefore, the inductances can be calculated as:

$$L=L_1=L_2=\frac{U_{PV}+U_{C1}}{i_L{f}_{SW}\Delta i_L}D$$

(11)

$$L_3=\frac{V_{C2}\left(1-D\right)}{f_{SW}\Delta i_{L3}}$$

(12)

where f_sw is the switching frequency and i_L is the inductor current and can be calculated as:

$$i_L=\frac{1}{1+D}\left(i_{PV}-i_{O}D\right)$$

(13)

where i_O is the output current of the converter. The capacitors (C₁ and C₂) are designed by using the voltage ripples (ΔU_C), which are assumed to be 5–10% of the output or DC-link voltage of the capacitor [20]. Hence, the capacitances can be calculated as,

$$C_1=C_2=\frac{i_O}{f_{SW}\Delta U_C}$$

(14)

where voltage ripples (ΔU_C) is given as,

$$\Delta U_C=\left(\frac{U_{PV}}{1-D}\right)10\%$$

(15)

The main functionality of the DCL capacitor is to store or supply the surplus power demand during transience and to lower the DC ripples [13]. It is designed according to [21] as,

$$C_{DC}=\frac{P_{CDC}}{4\pi f_g{U}_{DC}\Delta U_{DC}}$$

(16)

where P_DC is the DCL power, ΔU_DC is the peak-to-peak voltage ripples, and f_g is the grid frequency.

2.2.4. Loss Analysis

Equivalent circuitries of proposed converters, including the parasitic resistances in switching interval (t₀ ~ t₁) and (t₁ ~ t₂) are presented in Figure 6a,b respectively. In the Figure 6a,b, the parasitic resistances of the components are considered as; (a) r_ONS is the resistance of the switch in turn ON state, (b) r_D1, r_D2, r_D3, r_D4, r_D5, and r_D6 are the ON-resistances of diodes D₁, D₂, D₃, D₄, D₅, and D₆, respectively, (c) U_D1, U_D2, U_D3, U_D4, U_D5, and U_D6 are the threshold voltages of D₁, D₂, D₃, D₄, D₅, and D₆, respectively, (d) r_L1, r_L2, and r_L3 are the equivalent ESRs of inductors L₁, L₂, and L₃, respectively, and (e) r_C1, r_C2, and r_CDC are the ESR of capacitors C₁, C₂, and C_DC, respectively.

• Inductor Copper Loss

The copper loss of inductor is given as,

$$P_L=2i_{L-A}^2 r_L+i_{L3-A}^2{r}_L$$

(17)

where i_L−A and i_L3−A are the average current of L (L₁ = L₂ = L hence r_L1 = r_L2 = r_L) and L₃, respectively. Solving (17) would yield us to:

$$P_L={\left(\frac{1}{1+D}\left(i_{PV}-i_{O}D\right)\right)}^2{r}_L$$

(18)

• Capacitor Loss

The power loss in the capacitor mainly depends on the Root Mean Square (RMS) value of the current flowing through capacitor and ESR of capacitor. Moreover, as C₁ and C₂ are of same rating thus r_C1 = r_C2 = r_C. The power loss can be calculated as,

$$P_C=\left(i_{C1-R}^2 +i_{C2-R}^2\right) r_C+i_{CDC-R}^2 r_{CDC}$$

(19)

Solving (19) in term of duty cycle would give us:

$$P_C=\left(\frac{2i_O^2+i_L^2-2i_O{i}_L}{D\left(1-D\right)}\right)r_C+\left(\frac{i_O^2}{D}\right)r_{CDC}$$

(20)

• Switch Loss

There are two types of switch losses, i.e., conduction loss and switching loss and can be given as:

$$P_{S-Total}=P_{S-Swt}+P_{S-Cond}$$

(21)

The switching loss depends on the turn ON and OFF time, peak current (i_S−P), switching frequency, and voltage appeared across switch (U_S). Hence, the switching power loss can be given as:

$$P_{S-Swt}=\frac{t_{ON}+t_{OFF}}{2}\left(U_S.i_{S-P}.f_{SW}\right)$$

(22)

Putting values in (22) and solve in term of duty cycle would give us:

$$P_{S-Swt}=\left(t_{ON}+t_{OFF}\right)\left(\frac{1+D}{1-D}\right)\left(\frac{\left(1-D\right)i_L-i_O}{D}\right)U_O.i_O.f_{SW}$$

(23)

The conduction loss of the switch can be calculated as:

$$P_{S-Cond}=i_{S-R}^2.r_{ONS}=2{\left(\frac{\left(1-D\right)i_L-i_O}{D}\right)}^2{i}_O^2.r_{ONS}$$

(24)

where i_S−R is the RMS current of S.

• Diode Loss

The forward voltage drop and the conduction loss are the two types of losses associated with the diode.

$$P_{D-Total}=P_{D-UD}+P_{D-Cond}$$

(25)

The forward voltage drop loss is given as:

$$P_{D-UD}=\left(i_{D1-A}+i_{D2-A}+i_{D3-A}+i_{D4-A}+i_{D5-A}+i_{D6-A}\right)U_D$$

(26)

where i_D1−A to i_D6−A are the average current flows through diodes D₁ to D₆, respectively. Solving (26) would give us:

$$P_{D-UD}=\left(2i_L+i_O\left(1+{\left(1+D\right)}^2\right)\right)U_D$$

(27)

The conduction loss of diodes is calculated as,

$$P_{D-Cond}=\left(i_{D1-R}^2+i_{D2-R}^2+i_{D3-R}^2+i_{D4-R}^2+i_{D5-R}^2+i_{D6-R}^2\right)r_D$$

(28)

where i_D1−R to i_D6−R are the RMS current of diodes D₁ to D₆, respectively, where r_D is the equivalent ON-resistance of diodes. Solving (28) in term of duty cycle would yield us to:

$$P_{D-Cond}=\left(1-D\right)i_{PV}^2+\left(1+D\right)\left(i_L^2+i_{L3}^2\right)+\left(\frac{1}{D\left(1-D\right)}\right)i_O^2+\left(\frac{{\left(\left(1-D\right)i_L-i_O\right)}^2}{1-D}\right)r_D$$

(29)

• Total Loss

The total loss of the proposed converter can be calculated as:

$$P_{Loss}=P_L+P_C+P_{S-Swt}+P_{S-Cond}+P_{D-Vf}+P_{D-Cond}$$

(30)

The efficiency of the converter is obtained as:

$${\eta }_{Converter}=\left(\frac{P_o}{P_o+P_{Loss}}\right)100\%$$

(31)

2.2.5. Comparative Analysis

A comparative analysis of the proposed converter with the conventional and newly developed topologies on the basis of some main indicators such as capacitors, inductors, diodes, and switches count, are listed in

Table 1. Comparative analysis of proposed converter with other converters.

Topology	Switches	Diodes	Inductors	Capacitors	Passive	Total	Voltage Gain	Voltage Stress on Switch
Cuk, SEPIC, Zeta	1	1	2	2	4	6	$\frac{D}{1-D}$	$\frac{1}{1-D}$
[6]	1	7	4	2	6	14	$\frac{2D}{1-D}$	$\frac{1+D}{1-D}$
[8]	1	3	4	6	10	14	$\frac{3D}{1-D}$	$\frac{1}{1-D}$
[22]	2	5	3	4	7	14	$\frac{3D-D^2}{1-D}$	$\frac{3-D}{1-D}$
[23]	2	7	4	1	5	14	$\frac{1+3D}{1-D}$	$\frac{D}{1-D}$
[24]	1	8	4	3	7	16	$\frac{1+3D}{1-D}$	$\frac{1+D}{1-D}$
[25]	2	4	4	6	10	16	$\frac{1+3D}{1-D}$	$\frac{1+D}{1-D}$
[26]	1	3	3	5	8	12	$\frac{3D}{1-D}$	$\frac{D}{1-D}+1$
Proposed	1	6	3	3	6	13	$\frac{{\left(1+D\right)}^2}{1-D}$	$\frac{1+D}{1-D}$

. Moreover, the comparative analysis of the voltage conversion ratio and voltage stress on switch are sketched in Figure 7a,b, respectively. A topology presented in [6] has used one more component than the proposed converter but it cannot attain a high voltage gain as at 90% duty cycle its voltage conversion ratio is 18 and its switch also suffers from high voltage stress. A topology presented in [8] attains a high conversion ratio (i.e., at 90% duty the conversion ratio is 27) as compared to [6] but low compared to the proposed topology, despite it using one more inductor. However, the voltage stress across the switch is lower compared to the proposed converter. A converter proposed in [22] attains a low voltage conversion ratio and a switch suffers from a very high voltage stress. Moreover, the topologies proposed in [23,24,25] attain a high voltage gain compared to the proposed one, i.e., at 90% duty cycle they all attain a voltage gain of 37, while the proposed converter attains a conversion ratio of 36.1. However, these topologies have used more components and the switch suffers from high voltage stress. The topology in [26] has low component count and voltage stress on a switch compared to the proposed converter but it is unable to attain a high voltage conversion ratio. From the above discussion and from Figure 7a,b, it can be observed that most of the topologies have low voltage conversion ratio and high voltage stress on a switch as compared to the proposed topology.

3. Inverter Controller Design

A 2nd stage of the PV configuration system consists of DC–AC inverter, LCL filter, and a grid as shown in Figure 1. The most important part in the 2nd stage is the control of the inverter that is implemented in the form of two cascaded loops, i.e., inner and outer loop. In the proposed model, the dual loop control architecture is implemented using a stationary reference frame (αβ), as presented in Figure 8 [27]. The voltages and currents are transformed from abc frame to αβ frame as:

$$\left[\begin{array}{c}{U}_{\alpha }\\ U_{\beta }\end{array}\right]=\frac{2}{3}\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}{U}_a\\ U_b\\ U_c\end{array}\right]$$

(32)

$$\left[\begin{array}{c}{i}_{\alpha }\\ i_{\beta }\end{array}\right]=\frac{2}{3}\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$$

(33)

Initially, the measured DCL voltage is compared with the reference to generate an error. The error is then subjected to the voltage control block where different controllers such as PI, FOPI, API, and AFOPI are used for DCL regulation. A PR controller is implemented in the inner loop to generate the voltage reference. The desired voltage generated by the current controller has transformed again to abc reference frame, which is used to generate the PWM for the inverter.

3.1. DC-Link Voltage Regulation

In this research, BP algorithm-based API and AFOPI controllers are designed that dynamically update the control parameters in case of any disturbance or uncertainty and maintain a constant voltage at DCL. These controllers are discussed below in this section.

3.1.1. Adaptive PI Controller

To regulate a DCL voltage, a PI controller according to [10] is given as:

$$U_{CDC}^{*}/i_g^{*}=k_{p}e\left(t\right)+k_i\int e\left(t\right) dt$$

(34)

where U_DC*/i_g* is the controller output, e (error) is the controller input and is defined as e = U_CDC* − U_CDC, k_p is the proportional gain, and k_i is the integral gain. From (34), it can be observed that the values of k_p and k_i are fixed and unable to change in case of parametric variations. Therefore, the performance of the PV system will be greatly affected. To tackle the above discussed problems, in this research work, a Back Propagation (BP) algorithm-based API is designed [28]. A BP optimization technique uses a gradient descent function as it measures all the changes in weights according to change in error and is defined as,

$$J=\frac{1}{2}{e}^2$$

(35)

The gain of BP algorithm is given as,

$$k_{new}=-\gamma ex$$

(36)

where k_new $\in$ {k_p-new, k_i-new}, γ presents the learning rate, and x is the input parameter of k. The BP algorithm is used to improve the transient response and minimize the error. The learning procedure and updated parameters are defined as,

$$k_{p-new}=-\gamma e{x}_1 and k_{i-new}=-\gamma e{x}_2.$$

(37)

where x₁ and x₂ are the input parameter for k_p-new and k_i-new, respectively. The anticipated updated values of k_p-UP and k_i-UP can be calculated as,

$$k_{p-UP}=k_p+K_{p-new}=k_p-\gamma e{x}_1$$

(38)

$$k_{i-UP}=k_i+K_{i-new}=k_i-\gamma e{x}_2$$

(39)

The updated values of k_p-UP and k_i-UP enable the DC-link voltage to return to the condition where the steady state error is almost zero. Hence, the API controller can be defined as,

$$U_{DC}^{*}/i_g^{*}=k_{p-UP}e\left(t\right)+k_{i-UP}{\displaystyle \int e\left(t\right)} dt$$

(40)

Using (38) and (39) in (40), we produce the API controller as,

$$U{}_{DC}^{*}/i_g^{*}=\left[k_p-\gamma x_1{e}^2\left(t\right)dt\right]+\left[k_i-\gamma e{x}_2{\displaystyle \int e\left(t\right)} dt\right]$$

(41)

3.1.2. Adaptive FOPI Controller

To regulate a DCL voltage, an FOPI controller used in [11] is given as:

$$U_{DC}^{*}/i_g^{*}=k_{p}e\left(t\right)+k_i{D}_t^{-\lambda }{\displaystyle \int e\left(t\right)} dt$$

(42)

whereas λ is any arbitrary real number. Compared to PI controller, in FOPI controller, three parameters (k_p, k_i, and λ) are required to be designed. Thus, this modification increases the system flexibility and accuracy. However, the issue of fixed parameters of the FOPI persists, therefore, the FOPI controller is made adaptive according to the procedure discussed for API controller (see Section 3.1.1). Thus, the AFOPI controller is given as,

$$U_{DC}^{*}/i_g^{*}=\left[k_p-\gamma x_1{e}^2\left(t\right)dt\right]+ \left[k_i-\gamma e{x}_2{D}_t^{-\lambda }{\displaystyle \int e\left(t\right)} dt\right]$$

(43)

3.2. Current Controller

A simplified diagram of PR controller presented in Figure 9 consists of proportional gain (k_p) that is added to the resonant path. The resonant path comprises of a resonant gain (k_ir) and a filter whose transfer function (TF) in z-domain is presented by H_r (z). A proportional gain is given as,

$$k_p=\frac{(\gamma )\sqrt{(\gamma )}{\omega }_r(L_i+L_g)-(R_i+R_g)}{U_{dc}/2}$$

(44)

Comparatively, γ = 2ξ + 1 and ξ is the damping factor and its value lies in the range of 0.9–1.0. L_i and R_i are the inverter side inductance and resistance of LCL filter, while the grid side incidence and resistance of an LCL filter are presented by L_g and R_g, respectively. U_CDC describes the DC-link voltage and ω_r represents the resonant angular frequency and ω_r = 2 × π × f_r, where f_r presents the resonant frequency. Moreover, ω_r must be equal to f_g because the controller acts in fundamental frequency for the accurate injection of active power in the grid. The value of k_ir and TF of resonant filter can be calculated as,

$$k_{ir}=\frac{{\omega }_r{}^2(L_i+L_g)\left({\gamma }^2-1\right)}{U_{DC}}$$

(45)

$$H_r\left(z\right)=\frac{b_0+b_1{z}^{-1}+b_2{z}^{-2}}{a_0+a_1{z}^{-1}+a_2{z}^{-2}}$$

(46)

where the coefficients of H_r (z) can be calculated from (47–52) according to [17,29] as,

$$b_0=k_r{B}_r{T}_a$$

(47)

$$b_1=\left[-k_r{B}_r{e}^{-0.5BrTa}\mathrm{Cos}\left(T_a\sqrt{{\omega }_r{}^2-0.25B_r{}^2}\right)-C\right]T_a$$

(48)

$$b_2=0$$

(49)

$$a_0=1$$

(50)

$$a_1=-2e^{-0.5B_r{T}_a}\cos \left(T_a\sqrt{{\omega }_r{}^2-0.25B_r{}^2}\right)$$

(51)

$$a_2=e^{-B_r{T}_a}$$

(52)

where k_r is the resonant gain, B_r = 2πBs is the resonant angular bandwidth, T_a is the sampling period, and C is constant defined in (53) as,

$$C=\frac{0.5k_r{B}_r{}^2}{\sqrt{{\omega }_r{}^2-0.25B_r{}^2}}{e}^{-0.5B_r{T}_a}\sin \left(T_a\sqrt{{\omega }_r{}^2-0.25B_r{}^2}\right)$$

(53)

The transfer function of the controller presented in (46) is simulated in MATLAB environment to check its stability by considering the parameters values presented in

Table 2. Parameters value of PV system.

Parameter	Value
Grid Voltage (Ug)	230 V rms
Grid frequency (fg)	60 Hz
Converter-side inductor (Li)	1.74 × 10−4 H
Converter-side resistance (Ri)	0.01 ohm
Grid-side inductor (Lg)	1.2 × 10−3 H
Grid-side resistance (Rg)	0.01 ohm
LCL capacitance (Cf)	3.31 × 10−5 F
LCL damping resistance (Rd)	20.5 ohm
DC-link voltage (UDC)	700 V
Grid resistance (Rs)	2 ohm
Grid inductance (Ls)	3 × 10−3 H
Switching frequency (fsw)	10 × 10−3 Hz
Sampling frequency (fa)	1/1 × 10−6 Hz
Sampling period (Ta)	1 × 10−6 s
Resonant frequency (fr)	60, 300 Hz
Resonant frequency bandwidth (Bs)	1.5
Resonant angular bandwidth (Br)	Br = 2πBs
Resonant gain (kr)	1
Damping factor (ζ)	0.95

. The magnitude and phase response of the resonant filter are shown in Figure 10a. The efficiency and accurate performance of the filter can be observed that at only 60 Hz the gain turns to 0 dB. It means that only the elements at 60 Hz are multiplied by 01 while all other components are attenuated significantly and cannot pass through the filter. Moreover, a phase shift of 180° is observed at the resonant frequency due to the placement of poles of TF. Similarly, the magnitude and phase response of the proposed PR controller is presented in Figure 10b. Unlike the resonant filter, the highest amplification occurs at 60 Hz and is equal to 47.4 dB. Moreover, similar to the filter response, a phase shift of 180° is also observed at 60 Hz. The overall procedure of designing a proposed controller can be summarized in Figure 11.

4. Results and Discussion

To validate the effectiveness of theoretical and analytical concepts of the proposed system, it is simulated in MATLAB and Simulink software. In this section, the results of the proposed system are discussed for two parts. In the first part, the simulation results of the proposed DC–DC converter are carried out while in the second part the simulation results of the whole PV system are conducted and discussed.

4.1. Simulation Results of DC–DC Converter

To validate the effectiveness and the theoretical analysis of the proposed DC–DC converter presented in Section 2, the converter is simulated according to the components’ values presented in

Table 3. Component values of DC–DC converter.

Components	Values
Input Voltage	70 V
Output Voltage	705 V
Inductors (L1 and L2)	205 × 10−6 H
Inductor (L3)	180 × 10−6 H
Capacitors (C1 and C2)	2.2 × 10−6 F
Capacitor (CDC)	450 × 10−6 F
Duty Cycle	71%
Switching Frequency	24 kHz
Load Resistance	100 Ω

(note that the Table 3 values are only limited to Section 4.1). In this simulation, the PV system is considered as an independent DC voltage source that generates a DC voltage of 70 V as presented in Figure 12a. The duty cycle of the switch is set to 71% as depicted in Figure 12b, so that the converter can attain a voltage conversion ratio of 10 and a voltage of 700 V is achieved at the output port, as the output voltage is equal to the sum of voltages across C₁ and C₂, according to Equation (1). From Figure 12c, it can be observed that a 297 V and 408 V appeared across C₁ and C₂ according to Equations (3) and (5), respectively, which creates a total of 705 V at the output as shown in Figure 12d. The switching voltage on the semiconductor devices such as U_S, U_D4, and U_D6 is equal to 408 V as presented in Figure 12e,f, which satisfies the calculated values in Equation (7). In a similar manner, a switching voltage across D₁, D₃, D₂, and D₅ are presented in Figure 12g–i, respectively. From these results, it can be concluded that the proposed converter attains a high voltage gain with low duty cycle and with reduced voltage stress on diodes and the switch.

4.2. Simulation Results of Overall PV System

To validate the theoretical concepts of the proposed DC–DC converter along with the dual control loops, a PV system is simulated in MATLAB and Simulink software according to the feed-forward control architecture presented in Figure 8. The simulation is prepared according to the parameters listed in Table 3. Figure 13a shows the temperature and irradiance (T&G) of the PV panel. At the start of the simulation, the values of T&G are kept at 800 W/m² and 25 °C. At time 1.0 s, the system is subjected to disturbance (due to the intermittent nature of the PV system) and the values of T&G change to 600 W/m² and 30 °C. Similarly, at t = 2 s, the T&G values change again to 1000 W/m² and 20 °C. To extract the maximum power from the PV array, a P&O technique is used, and the PV output voltage, current, and power according to these changes are presented in Figure 13b–d, respectively. From Figure 13b, it can be observed that the PV output voltage is very low and varies according to environmental conditions and cannot be used as an input for the inverter.

Therefore, this low generated PV voltage is amplified by using a proposed high gain DC–DC converter. However, to maintain a constant DC-link voltage, this amplified voltage needed to be regulated. For this purpose, PI, FOPI, API, and AFOPI controllers are used and their comparative performances are presented in Figure 13e while the values of the controllers gain are listed in Table A2. From the zoom-in view, it can be observed that the conventional PI controller has the worst performance in terms of tracking accuracy and dynamic response and is then followed by the FOPI controller. Both these controllers have fixed parameters that need to be updated according to the disturbances, therefore, the proposed API and AFOPI controllers are developed. It can be seen that both the proposed controllers have considerably improved the tracking accuracy, dynamic response, and eliminated the zero steady-state error. At t = 2 s, the spike in the VDC reaches approximately to 780V (PI), 740V (FOPI), 710V (API), and 705V (AFOPI). Moreover, the PI and FOPI controllers take almost 0.2 s, while API and AFOPI controller takes 0.1 s to reach its steady-state condition. Hence, the proposed API and AFOPI controllers are fast, less sensitive to disturbance, and more robust compared to the conventional PI and FOPI.

For better understanding and clarity, the grid injected current waveforms are presented in a case when an AFOPI controller is applied in the outer voltage loop. The 3Φ grid injected current for the varying climatic conditions is presented in Figure 13f whereas a single-phase current (i_b) is presented in Figure 13g. According to Figure 13a, the variation in T&G occurs at every 1 s accordingly. If we examine the zoom-in view of Figure 13g, the current controller acts accordingly and tracks its reference rapidly with zero steady-state error. Moreover, to analyze the total harmonic distortion, a current waveform starting from 1.1 s to almost 10 cycles is also presented in Figure 13g. It can be examined that the proposed PR controller results in only 1.82% of THD and efficiently removes the harmonic contents. The simulation results guaranteed the smooth and stable performance of the proposed system.

5. Conclusions

In this research work, a single switch non-isolated hybrid DC–DC converter is proposed. It attains a high voltage conversion ratio without the use of a transformer or extreme high duty cycle. The usage of a single switch makes its control simple hence the cost is considerably reduced. Moreover, due to hybrid structure and low voltage stress on semiconductor components, a proposed converter attains high efficiency compared to classical converters at high duty cycle. The operating principle, steady-state and comparative analysis of the proposed converter are also discussed. From the comparative analysis and simulation results, it is concluded that the proposed converter attains a high step-up conversion ratio with a low duty cycle, and reduced component count.

In the 2nd stage of the PV system, API and AFOPI controllers are employed in the outer voltage control loop to regulate the DC-link voltage in case of PV intermittency. Compared to the conventional PI and FOPI (having fixed parameters), the proposed controllers ensure (a) high tracking accuracy and efficiency, (b) fast dynamic response, (c) reduction in steady-state error, (d) reduced fluctuation in DC-link voltage during the transient state, and (e) less sensitivity to sudden disturbances. Furthermore, a PR controller is used in the inner control loop. In the proposed PR controller, there is a unique equation for every parameter, hence no parameter is computed empirically or by a trial-and-error method such as a conventional PR controller. The Bode diagram of the controller is plotted according to pre-indicated desired parameters. From the result, it is concluded that the controller accurately follows its reference with zero steady-state error, unpredictable behavior, and results in high-quality grid injected current.