# Parallel Power Sharing Control of Multi-Controllable Rectifiers in a High-Power DC Fast Charging Station

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

- (1)
- The power sharing controller parameters based on virtual impedance control are designed, including the current loop, voltage loop proportional integral (PI) controller parameters, and virtual impedance parameters. Considering the bandwidth and stability of the current loop and voltage loop, the parameters of the PI controller are designed. According to the principle of shielding the natural output impedance of the system and ensuring the fluctuation range of the DC bus voltage, the virtual impedance is designed to realize the stability of the DC bus voltage and the power sharing of multiple controllable rectifier modules.
- (2)
- Considering that an EV can be equivalent to a constant power load when it is charged with a constant current, a constant voltage-controlled Buck converter with a resistive load is used to simulate the constant power load, and a mathematical model of its input impedance is established. Using the impedance analysis method, the cascaded system composed of multiple parallel controllable rectifier modules and a DC–DC converter is used to study the maximum load that can be tolerated when EV is charged with a constant current.

## 2. High-Power DC Fast Charging Station Topology and Controller Structure

_{s}. The modules adopt a three-phase half-bridge topology, and their DC sides are connected in parallel to the same DC bus through the inductor L that suppresses the impact of the parallel current. The DC–DC converter connected to the DC bus is connected to the EV battery, and the output voltage of the DC–DC converter can be controlled to adapt to the charging voltage of different types of EV batteries, providing fast charging with a maximum power of 180 kW.

_{dc}, the outlet current, i

_{dc}, of each module, and the grid-side voltage, u

_{abc}, and current, i

_{abc}. The controller of each module adopts a double-loop structure. The inner loop is the current loop, and the i

_{abc}is converted to the d–q coordinate system and is controlled by the PI controller. The q-axis controller is ignored because the system is at a unity power factor (i.e., the current reactive component reference value i

_{q}* = 0), and the voltage active power control is mainly affected by the d-axis active current. The outer loop is a voltage loop based on virtual impedance control, Z

_{v}is the virtual impedence and V

_{dc}* is the reference value of the DC bus voltage. The output of the voltage loop PI controller is i

_{d}*, the reference value of the d-axis component, i

_{d}, of the current loop. Power sharing between different modules can be realized by designing the virtual impedance, Z

_{v}. The main circuit and controller transfer function model of each rectifier module are shown in Figure 3.

## 3. Parameter Design of the Power Sharing Controller

#### 3.1. Current Loop

_{m}is the transfer function of the SVPWM modulation module; G

_{id}is the transfer function from the duty cycle, d

_{d}, to the d-axis component of the AC side current, i

_{d}; G

_{idd}is the transfer function from the duty cycle, d

_{d}, to the output current, i

_{dc}; and G

_{ud}is the transfer function from the duty cycle, d

_{d}, to the DC side capacitor voltage, u

_{c}; G

_{Pii}is the PI controller in the inner current loop; G

_{Piu}is the PI controller in the outer voltage loop. The transfer functions of G

_{m}, G

_{id}, G

_{ud}, and G

_{idd}can be expressed as:

_{d}is the d-axis component of the duty cycle; i

_{d}is the d axis components of the AC side inductor current; u

_{c}is the DC side capacitor voltage; i

_{dc}is the output current of the DC side; u

_{d}is the d axis components of u

_{abc}; i

_{d}

^{*}is the inner current reference value; D

_{d}, I

_{d}, and U

_{c}are the corresponding steady-state operating points; L

_{s}is the AC side inductance; R

_{s}is the equivalent resistance of the AC side; C is the DC side capacitor; L is the paralleled inductance; R

_{L}is the load resistance; V

_{dc}is the DC bus voltage; Z

_{v}is the virtual impedance.

_{io}in the current loop controller from i

_{d}

^{*}to i

_{d}can be expressed as:

_{io}in the current loop controller from i

_{gd}

^{*}to i

_{gd}can be expressed as:

_{pi}and integral coefficient k

_{ii}of the PI controller, as shown in Figure 4 and Table 1. With the increase in k

_{pi}, the response speed of the current loop becomes faster, the overshoot of the system decreases, the phase angle margin becomes larger, and the stability becomes better. With the increase in k

_{ii}, the response speed of the current loop becomes faster, the overshoot increases, and the phase angle margin decreases slightly. Considering the dynamic performance and steady-state performance of the current loop, the final choice is k

_{pi}= 3.5, k

_{ii}= 100. When k

_{pi}= 3.5 and k

_{ii}= 100, the frequency bandwidth of the current loop is 2.28 kHz, and the phase angle margin is 88.5 deg, while the response time is 0.0006 s, the overshoot σ% = 0, and the steady-state error is 0.0015.

#### 3.2. Voltage Loop

_{uo}in the voltage loop controller from V

_{dc}* to V

_{dc}can be expressed as:

_{uc}in the voltage loop controller from V

_{dc}* to V

_{dc}can be expressed as:

_{pu}and integral coefficient k

_{iu}in the PI controller, as shown in Figure 5 and Table 2. Within a certain range, with the increase of kpu, the response speed of the voltage loop becomes faster, and the phase angle margin first increases and then decreases. As kiu increases, the response speed of the voltage loop becomes faster, the phase angle margin decreases slightly, and the overshoot increases. Considering the dynamic performance and steady-state performance of the current loop, the final choice is k

_{pu}= 1.7 and k

_{iu}= 150. When k

_{pu}= 1.7 and k

_{iu}= 150, the bandwidth in the voltage loop is 42.68 Hz, the phase margin is 112 deg, and the gain margin is 13.7 dB, while the response time is 0.14 s, the system has no overshoot, and the steady-state error is 0.001.

#### 3.3. Virtual Impedance

_{no}from i

_{dc}to V

_{dc}can be expressed as:

_{no}is shown in Figure 6. As k

_{pu}increases, the gain margin of Z

_{no}will decrease and the system will become unstable. Z

_{no}is inductive in the low-frequency band and capacitive in the high-frequency band. It can be seen from Figure 6b that k

_{iu}has little effect on system stability.

- (1)
- The virtual impedance Z
_{v}must be greater than the natural output impedance Z_{no}to reduce the influence of natural impedance on the power sharing amongst different modules; - (2)
- The droop in the DC bus voltage after adding the virtual impedance cannot exceed 5% of the rated voltage when the load power changes from 30% rated power to full-load;
- (3)
- It is necessary to consider the load capacity of the system. If the virtual impedance is designed to be too large, it will increase the output impedance of the source and reduce the overall load capacity of the system.

_{dc}is selected as 750 V. When the load power is at 30% of the total load, the bus voltage rise should be less than 5%. Similarly, when the load power is at the rated value, the bus voltage should drop by less than 5%. According to Figure 6a, the virtual impedance Z

_{v}can be determined by:

_{ov}of the system after adding the virtual impedance is as follows:

_{ov}after adding the virtual impedance is shown in Figure 7b. Z

_{ov}is purely resistive in the low-frequency band. The magnitude of Z

_{ov}is dominated by its droop coefficient such that the effect of the natural impedance, Z

_{no}, in the low-frequency band can be basically ignored. Therefore, considering the above design principles of Z

_{v}, this article sets the virtual impedance Z

_{v}of each 60 kW module to be 0.2 Ω.

## 4. Analysis of the Load Capacity of the Cascaded System

#### 4.1. Input Impedance of a Constant Power Load

_{in}is the input current; L

_{L}is the load side inductance; i

_{L}is the current flowing through it; R

_{L}is the resistive load; r

_{L}is the internal resistance of L

_{L}; C

_{L}is the load side capacitance, u

_{L}is the load voltage; d

_{L}is the duty cycle of the switch tube. The linearized small signal model at the steady-state operating point (V

_{dc}, D

_{L}, I

_{L}, U

_{L}) is:

_{i}is the transfer function from input voltage, u

_{in}, to the input current, i

_{in}; G

_{uuL}is the transfer function from u

_{in}to load side voltage, u

_{L}; T

_{id}is the transfer function from duty cycle, d

_{L}, to i

_{in}; G

_{udL}is the transfer function from d

_{L}to u

_{L}; G

_{PIuL}is the voltage PI controller transfer function.

_{in}, of the constant power load is:

_{in}of constant power load is:

#### 4.2. Analysis of Load Capacity

_{m}, which can be determined by the ratio of the output impedance, Z

_{o}, of the source to the input impedance, Z

_{in}, of the load. The Nyquist curve of T

_{m}and the frequency-domain response of input impedance, Z

_{in}, and output impedance, Z

_{o}, are shown in Figure 11.

_{N}= 180 kW) increases, the cascaded system could become unstable. According to the Nyquist stability criterion, when P = 1.338P

_{N}, the Nyquist curve surrounds the (−1, j0) point, indicating that the cascade system is unstable. Therefore, the maximum load capacity of the cascaded system is 240.8 kW. The frequency–domain response of input impedance, Z

_{in}, and output impedance, Z

_{o}, is shown in Figure 11b; when P = 1.338P

_{N}, the resonance frequency of system is 53.66 Hz.

## 5. Simulation and Experimental Results

#### 5.1. Simulation Results

_{1}, P

_{2}, P

_{3}, and output current, i

_{dc1}, i

_{dc2}, i

_{dc3}, of the three rectifier modules are shown in Figure 12. Because the virtual impedances of the three modules are the same, during the dynamic and steady-state process when the EV charging load increases from 90 kW to 180 kW, the three modules can achieve power sharing, and the output currents remain the same.

_{N}to 1.0P

_{N}and 1.3P

_{N}, the DC bus voltage can remain stable. When it increases to 1.4P

_{N}> 1.338P

_{N}, the DC bus voltage becomes unstable, which means that the cascaded system cannot bear such a large constant power load. This is consistent with the previous impedance analysis results.

#### 5.2. Experimental Results

_{1}, P

_{2}and P

_{3}are shown in Figure 16a. The waveforms of output currents i

_{dc1}, i

_{dc2}and i

_{dc3}are shown in Figure 16b. The three modules can achieve dynamic and steady-state power sharing, and the output currents can remain the same.

## 6. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## Abbreviations

EV | Electric Vehicle |

AC/DC | Alternating Current/Direct Current |

THD | Total Harmonic Distortion |

PFC | Power Factor Correction |

DAB | Dual Active Bridge |

ZVS | Zero-Voltage Switching |

IPQR | Improved Proportional Quasi-Resonant |

PI | Proportional Integral |

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**Figure 4.**Bode diagram and step response of current loop changing with k

_{pi}and k

_{ii}. (

**a**) Bode diagram of G

_{io}changing with k

_{pi}. (

**b**) Step response of G

_{ic}changing with k

_{pi}. (

**c**) Bode diagram of G

_{io}changing with k

_{ii}. (

**d**) Step response of G

_{ic}changing with k

_{ii}.

**Figure 5.**Bode diagram and step response in voltage loop changing with k

_{pu}and k

_{iu}. (

**a**) Bode diagram of G

_{uo}changing with k

_{pu}. (

**b**) Step response of G

_{uc}changing with k

_{pu}. (

**c**) Bode diagram of G

_{uo}changing with k

_{iu}. (

**d**) Step response of G

_{uc}changing with k

_{iu}.

**Figure 6.**Frequency–domain response of output impedance, Z

_{no}. (

**a**) Frequency–domain response of Z

_{no}when k

_{pu}changes. (

**b**) Frequency–domain response of Z

_{no}when k

_{iu}changes.

**Figure 7.**Virtual impedance design. (

**a**) Virtual impedance design principle. (

**b**) Output impedance after adding virtual impedance.

**Figure 11.**Nyquist curve and frequency–domain response of the cascaded system. (

**a**) Nyquist curve of T

_{m}when the load P changes. (

**b**) Input impedance Z

_{in}and output impedance Z

_{o}when P = 1.338P

_{N}.

**Figure 12.**Output power and currents of the rectifier modules. (

**a**) Output power. (

**b**) Output current.

**Figure 16.**Output power and currents of the rectifier modules. (

**a**) Output power. (

**b**) Output current.

**Table 1.**Dynamic and steady-state performance indicators of the current loop when k

_{pi}and k

_{ii}change.

k_{ii} = 100 | ||||||

k_{pi} | Gain Margin (dB) | Phase Margin (deg) | Bandwidth(kHz) | Overshoot (%) | Response Time | Steady-State Error |

0.01 | −9.85 | −9.93 | 0.14 | unstable | unstable | unstable |

0.1 | Inf | 26.1 | 0.15 | 5 | 0.06 | 7.8 × 10^{−4} |

1 | Inf | 83.5 | 0.66 | 0.22 | 0.05 | 1.8 × 10^{−3} |

3.5 | Inf | 88.5 | 2.28 | 0 | 6 × 10^{−4} | 1.5 × 10^{−3} |

7 | Inf | 89.3 | 4.55 | 0 | 3 × 10^{−4} | 6.4 × 10^{−3} |

k_{pi} = 3.5 | ||||||

k_{ii} | Gain margin (dB) | Phase margin (deg) | Bandwidth(kHz) | Overshoot (%) | Response time | Steady-state error |

1 | Inf | 88.7 | 2.28 | 0 | 6 × 10^{−4} | 5.5 × 10^{−3} |

10 | Inf | 88.6 | 2.28 | 0 | 6 × 10^{−4} | 5.7 × 10^{−3} |

100 | Inf | 88.5 | 2.28 | 1 | 6 × 10^{−4} | 1.5 × 10^{−3} |

300 | Inf | 88.2 | 2.28 | 1.5 | 4 × 10^{−3} | 3.9 × 10^{−2} |

1000 | Inf | 87 | 2.28 | 3.2 | 0.012 | 6 × 10^{−4} |

**Table 2.**Dynamic and steady-state performance indicators of the voltage loop when k

_{pu}and k

_{iu}change.

k_{iu} = 150 | ||||||

k_{pu} | Gain Margin (dB) | Phase Margin (deg) | Bandwidth (Hz) | Overshoot (%) | Response Time (s) | Steady-State Error |

0.1 | 18.1 | 75.2 | 14.5 | 0 | 0.07 | 5.2 × 10^{−3} |

1 | 17.4 | 96.4 | 17.8 | 0 | 0.09 | 5.2 × 10^{−4} |

1.7 | 13.7 | 112 | 42.7 | 0 | 0.14 | 4 × 10^{−4} |

3 | 9.23 | 71.6 | 86.1 | 0 | 0.16 | 1 × 10^{−3} |

7 | 2.21 | 12.9 | 152.7 | 46.5 | 0.35 | 5 × 10^{−4} |

10 | −0.816 | −4.54 | 192.7 | unstable | unstable | unstable |

k_{pu} = 1.7 | ||||||

k_{iu} | Gain margin (dB) | Phase margin (deg) | Bandwidth (Hz) | Overshoot (%) | Response time (s) | Steady-state error |

10 | 14.7 | 137 | 27.7 | 0 | 2.5 | 1.15 × 10^{−3} |

100 | 14.1 | 120 | 37.4 | 0 | 0.25 | 3.5 × 10^{−4} |

150 | 13.7 | 112 | 42.7 | 0 | 0.14 | 4 × 10^{−4} |

300 | 12.4 | 89.4 | 51.6 | 0 | 0.06 | 2.1 × 10^{−3} |

1000 | 4.24 | 20.9 | 77.5 | 54.3 | 0.1 | 1.3 × 10^{−3} |

Each Rectifier Module Parameters | Value |
---|---|

RMS value of grid line voltage V_{g}/V | 380 |

Filter inductor L_{s}/mH | 0.3 |

DC side capacitance C/mF | 1 |

Inductors connected in parallel L/mH | 1 |

The internal resistance of the inductance connected in parallel R/Ω | 0.001 |

Current loop PI controller parameters/k_{pi}, k_{ii} | 3.5, 100 |

Voltage loop PI controller parameters/k_{pu}, k_{iu} | 1.7, 150 |

Rated power P_{N}/kW | 60 |

Virtual impedance Z_{v}/Ω | 0.2 |

Reference value of DC bus voltage V_{dc}*/V | 750 |

Buck converter parameters | Value |

Filter inductor L_{L}/mH | 3.33 |

Filter inductor internal resistance r_{L}/Ω | 0.001 |

Load side capacitance C_{L}/mF | 0.2 |

Reference value of load voltage U_{L}*/V | 500 |

Voltage loop PI controller parameters/k_{puL}, k_{iuL} | 0.0005, 0.4 |

Each Rectifier Module Parameter | Value |
---|---|

RMS value of grid line voltage V_{g}/V | 380 |

Filter inductor L_{s}/mH | 0.5 |

DC side capacitance C/mF | 2 |

Inductors connected in parallel L/mH | 0.5 |

The internal resistance of the inductance connected in parallel R/Ω | 0.02 |

Current loop PI controller parameters/k_{pi}, k_{ii} | 3, 200 |

Voltage loop PI controller parameters/k_{pu}, k_{iu} | 1, 100 |

Rated power P_{N}/kW | 20 |

Virtual impedance Z_{v}/Ω | 0.1 |

Reference value of DC bus voltage V_{dc}*/V | 750 |

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## Share and Cite

**MDPI and ACS Style**

Xiao, Z.-X.; Cao, J.-N.; Zhu, H.-C.; Li, P.; Xue, H.-F.; Zheng, G.-X.; Jia, J.-W.
Parallel Power Sharing Control of Multi-Controllable Rectifiers in a High-Power DC Fast Charging Station. *World Electr. Veh. J.* **2023**, *14*, 193.
https://doi.org/10.3390/wevj14070193

**AMA Style**

Xiao Z-X, Cao J-N, Zhu H-C, Li P, Xue H-F, Zheng G-X, Jia J-W.
Parallel Power Sharing Control of Multi-Controllable Rectifiers in a High-Power DC Fast Charging Station. *World Electric Vehicle Journal*. 2023; 14(7):193.
https://doi.org/10.3390/wevj14070193

**Chicago/Turabian Style**

Xiao, Zhao-Xia, Jia-Ning Cao, Hong-Chi Zhu, Pan Li, Hao-Fei Xue, Guo-Xi Zheng, and Jiang-Wei Jia.
2023. "Parallel Power Sharing Control of Multi-Controllable Rectifiers in a High-Power DC Fast Charging Station" *World Electric Vehicle Journal* 14, no. 7: 193.
https://doi.org/10.3390/wevj14070193