# Control of Dual-Output DC/DC Converters Using Duty Cycle and Frequency

^{1}

^{2}

^{3}

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## Abstract

**:**

## 1. Introduction

#### 1.1. Research Motivations

_{2}emissions globally [1], the reduction of CO

_{2}emissions from vehicles is an effective measure to curb global warming. In an attempt to reduce CO

_{2}emissions, the vehicle market is switching from gasoline cars to electric vehicles (EVs), plug-in hybrid vehicles (PHVs) and fuel cell vehicles (FCVs), which are equipped with high-voltage sources that enable motor driving. The market for such vehicles is expected to grow continually in the coming years [2]. The auxiliary power sources of EVs, PHVs and FCVs use isolated DC/DC converters with input that provides high-voltage power for driving [3,4]. With the electrification of conventional functions (drive by wire) and the sophistication of internal environments, the number and types of auxiliary loads are increasing continually. That is, the power capacity required for the auxiliary power supply is increasing and, depending on the use conditions of the car, the power consumption of the auxiliary load may have a significant impact on the total vehicle power consumption [5,6]. One factor that increases the power consumption is the additional conduction losses caused by the large current that flows when a heavy load is driven with a 12 V power supply. An option for reducing these conduction losses is to set the power supply voltage of the auxiliary system to 48 V and to reduce the current value [7,8]. However, owing to the costs, part supplies and maintenance service involved, it is difficult to make all loads for a 12 V power supply compatible with a 48 V power supply and, as a result, the demand for loads requiring a 12 V power supply remains. For this reason, the auxiliary power supply requires a dual system that supports both 48 V and 12 V.

#### 1.2. Literature Review

#### 1.3. Contribution

## 2. Overview of Proposed Control Method and Main Circuit Configuration

#### 2.1. Overview of Proposed Control Method and Main Circuit Configuration

_{out}

_{1}and V

_{out}

_{2}are controlled by two control factors, namely the duty cycle and frequency (period) with rectangular alternating voltage. This control method requires the main circuit to contain waveforms with a duty cycle and frequency, as well as elements with output voltages that vary according to the changes in the duty cycle and frequency. Therefore, in this study, the isolated DC/DC converter depicted in Figure 2 was adopted as a simple main circuit to validate the proposed control method. The isolation approach used consists of a transformer, the primary side of which is an input capacitor (C

_{in}) and an H-bridge inverter that is formed by the switching devices S1, S2, S3 and S4. The gate signals G1, G2, G3 and G4 are input to each switch, respectively. G1 to G4 generate a rectangular alternating voltage with the duty cycle and frequency control factors and this voltage is applied to the primary side of the transformer. On the secondary side of the transformer, a rectifier circuit of output voltage V

_{out}

_{1}consisting of diodes D11, D12, D13, D14, L

_{out}

_{1}and C

_{out}

_{1}and, similarly, a rectifier circuit of output voltage V

_{out}

_{2}consisting of D21, D22, D23, D24, L

_{out}

_{2}and C

_{out}

_{2}are connected in parallel. A series of resonant filters consisting of L

_{srA}, C

_{srA}, L

_{srB}and C

_{srB}are inserted between the latter diode bridge circuit and the transformer. This series resonant filter changes the impedance to an arbitrary value by operating the frequency and thereby controls the output voltage. To maintain the symmetry of the operation, the parameters of the two series resonant filters must have the same values. Impedance changes caused by frequency affect the impedances of both the series resonant filter and the subsequent smoothing filter. In this case, if L

_{sr}

_{1}= L

_{sr}

_{2}= L

_{sr}and C

_{sr}

_{1}= C

_{sr}

_{2}= C

_{sr}, the impedance of the series resonant filter (Z

_{sr}) to the frequency of the transformer voltage (f

_{tx}) and the impedance following the smoothing filter of the V

_{out}

_{2}side (Z

_{sm}

_{2}) can respectively be expressed as

_{tx}and R

_{out}

_{2}is the load resistance value of the V

_{out}

_{2}-side circuit. Considering that the frequency of the waveforms doubles after the diode bridge full-wave rectification, the frequency in Z

_{sm}

_{2}is doubled. With these values, Z

_{out}

_{2}, which is the impedance of the V

_{out}

_{2}-side circuit for f

_{tx}, can be approximated as

_{out}

_{2}(f

_{tx})| decreases or increases monotonically within the operating frequency range, f

_{tx}and |Z

_{out}

_{2}| exhibit a one-to-one relationship and V

_{out}

_{2}can be controlled by f

_{tx}. Moreover, as the side circuit V

_{out}

_{1}is a typical diode bridge rectifier circuit, V

_{out}

_{1}can be changed by the duty cycle of the secondary side voltage of the transformer (D

_{tx}). Therefore, V

_{out}

_{1}is mainly controllable by D

_{tx}and V

_{out}

_{2}is mainly controllable by f

_{tx}but changes in D

_{tx}affect V

_{out}

_{1}as well as V

_{out}

_{2}, whereas changes in f

_{tx}affect V

_{out}

_{2}as well as V

_{out}

_{1}. Thus, it is not possible to control V

_{out}

_{1}and V

_{out}

_{2}independently using D

_{tx}and f

_{tx}, respectively. However, by adding a gap in the response speed of both output voltages, it is possible to prevent interference in the control by D

_{tx}and f

_{tx}and to adjust both output voltages to the target values.

#### 2.2. Operating Principles of Proposed Control Method

_{fb}

_{1}and V

_{fb}

_{2}, which are obtained by dividing by V

_{out}

_{1}and V

_{out}

_{2}, respectively. V

_{fb}

_{1}and V

_{fb}

_{2}are input into the FPGA via the AD converter and the differences from the respective target values V

_{out}

_{1}* and V

_{out}

_{2}* are input into the PI calculation part (PI

_{1}and PI

_{2}). The output signal from PI

_{1}contains the information of the phase shift amount δ (α

_{δ}) required by the pulse width control to define D

_{tx}, whereas the output signal from PI

_{2}contains the information necessary to define f

_{tx}(α

_{T}). These signals are input into the pulse width and frequency control (PWFC) section and are converted into the switching signals G1′ to G4′, which contain the information of D

_{tx}and f

_{tx}needed for the transformer voltage to control V

_{out}

_{1}and V

_{out}

_{2}. Thereafter, a signal with a certain dead time provided to G1′ to G4′ is output from the FPGA and it is subsequently output to the gates of S1 to S4 via the isolated gate driver (G1 to G4).

_{T}is generated by a counter inside the PWFC to generate these signals. This sawtooth wave counter decreases from the upper limit defined by α

_{T}and when the counter reaches zero it is set to the upper limit again. As the decrease ratio of the counter corresponds to the clock period (T

_{CLK}) of the FPGA and remains constant, the period of the sawtooth wave T

_{saw}(frequency f

_{saw}) is defined by α

_{T}. This is the period T

_{tx}(frequency f

_{tx}) that is necessary for the control. Furthermore, f

_{tx}is the switching frequency of G1′ to G4′ and is expressed as

_{T}is

_{MAX}and f

_{min}are the maximum and minimum values of the switching frequency, respectively. By turning a signal on when the counter reaches the upper limit (α

_{T}) and off when the counter reaches half of the upper limit (α

_{T/2}), it is possible to generate rectangular waveforms with a frequency corresponding to α

_{T}and a duty cycle of 0.5. This signal is designated as the G1′ signal.

_{δ}and the sawtooth wave counter. By turning G3′ on when the sawtooth waves become smaller than α

_{δ}and turning it off when the same amount of time since G1′ was turned on has elapsed, G3′ becomes a signal that is phase-shifted from G1′ by δ. Because the range of δ where the control holds is between 0° and 180°, the possible range of α

_{δ}is

_{txp},’ which is on the primary side voltage of the transformer generated by G1′ to G4′, D

_{tx}and T

_{tx}(=1/f

_{tx}) change according to the input values of α

_{T}and α

_{δ}. However, although f

_{tx}is determined uniquely by α

_{T}, D

_{tx}is not determined uniquely by α

_{δ}, because the sawtooth shape determined by α

_{T}is calculated by comparison with the counter.

## 3. Verification of Proposed Method Using Actual Circuit

#### 3.1. Circuit Specifications

_{out}

_{1}and V

_{out}

_{2}sides are expressed as P

_{out}

_{1}and P

_{out}

_{2}, respectively. The maximum value of the total output power, P

_{out}

_{1}+ P

_{out}

_{2}, was set to 1 kW and the maximum value of P

_{out}

_{2}was set to 500 W. The input voltage V

_{in}was set to 300 V, whereas the target values of the output voltages V

_{out}

_{1}and V

_{out}

_{2}were set to 48 V and 12 V, respectively. The minimum and maximum switching frequencies, f

_{min}and f

_{MAX}, were set to 50 kHz and 100 kHz, respectively and the FPGA used was a XC7K70T-1FBG484C with a clock frequency (f

_{CLK}) of 200 MHz (T

_{CLK}= 5 ns). When substituting the values of f

_{min}, f

_{MAX}and T

_{CLK}into Equation (5), α

_{T}can take values between 2000 and 4000. As α

_{T}is an integer, f

_{tx}and |Z

_{out}

_{2}| could take 2001 possible values under the verification control conditions. Proportional gains and time constants of PI

_{1}and PI

_{2}were K

_{1}= 2.5, K

_{2}= 0.5, τ

_{1}=3 µs, τ

_{2}= 8 µs, respectively.

_{in}was an aluminum electrolytic capacitor of 330 μF, the switching devices of the primary side H-bridge circuit (S1 to S4) were SiC MOSFET (SCT3030AL, ROHM) and the eight diodes of the secondary side diode bridge were SiC Schottky barrier diodes (FFSH4065A, ON Semiconductor). Because this circuit was designed to verify the proposed control method, the breakdown voltage and current capacity of these devices were substantially larger than necessary. The turn ratio of the transformer was 20:5. The parameters of the elements of the series resonant filter, L

_{sr}and C

_{sr}, were 4.5 μH and 560 nF, respectively. The output smoothing inductors were L

_{out}

_{1}= 7.3 μH and L

_{out}

_{2}= 7.0 μH, the output capacitor Cout1 was 88 μF with four ceramic capacitors of 22 μF in parallel and C

_{out}

_{2}was 188 μF with four ceramic capacitors of 47 μF in parallel. The values of C

_{in}, C

_{out}

_{1}and C

_{out}

_{2}are nominal values and the values of L

_{sr}, L

_{out}

_{1}and L

_{out}

_{2}are calculated by using the following equation:

_{0}, could be calculated as 100.3 kHz according to the following equation:

_{sr}and Z

_{sm}, which were then substituted into Equation (3). The result is presented in Figure 6. In this case, it was assumed that Rout2 → ∞. As indicated in Figure 6, the resonant frequency of the V

_{out}

_{2}-side circuit was approximately 100 kHz. It can be observed that this value was the resonant frequency of the resonant filter and it was not affected by the output smoothing LC filter. This is because the resonant frequency of the output smoothing LC filter (L

_{out}

_{2}, C

_{out}

_{2}) was approximately 4.4 kHz, which was far from 100.3 kHz. Moreover, the Q value of the output smoothing LC filter was less than 10% of the Q value of the series resonant filter (assuming that both filters had the same line resistance). As the resonant frequency required for control was approximately 100 kHz, in the operating frequency range between 50 kHz and 100 kHz, the impedance of the V

_{out}

_{2}-side circuit decreased monotonically as the frequency of the transformer voltage (f

_{tx}) increased, which enabled V

_{out}

_{2}to be controlled by f

_{tx}, as mentioned previously. The reason for the monotonic decrease instead of an increase is that the volume of L

_{out}

_{1}and L

_{out}

_{2}could be reduced with higher frequency when a large current passed (Z

_{out}

_{2}was small).

_{out}

_{2}-side circuit becomes narrower. Therefore, for the proposed control method to work as intended, it is necessary to select the most appropriate resonant frequency, operating frequency range, frequency–impedance characteristics and FPGA.

#### 3.2. Static Characteristics

_{out}

_{1}and V

_{out}

_{2}and output currents I

_{out}

_{1}and I

_{out}

_{2}, with a total output of 1,037 W (P

_{out}

_{1}= 461 W and P

_{out}

_{2}= 576 W), from power-up until reaching a steady state. The measurement devices used in the actual verification are listed in Table 2.

_{out}

_{1}and V

_{out}

_{2}were 48.0 V and 12.0 V, respectively, as per the target values. The ripple voltages in the steady state, V

_{out}

_{1}and V

_{out}

_{2}, were both ±0.6 V, whereas the ripple currents, I

_{out}

_{1}and I

_{out}

_{2}, were ±0.2 A and ±0.8 A, respectively. The ripple current I

_{out}

_{2}was larger because the resolution of TCP303 used to measure I

_{out}

_{2}was lower than that of the TCP312A used to measure I

_{out}

_{1}. These results indicate that the proposed control method can produce an output of 1 kW in an actual circuit.

#### 3.3. Operation Points

_{out}

_{1}side using inductive resistance, whereas four operation points of 142 W, 268 W, 394 W and 499 W were prepared on the P

_{out}

_{2}side using non-inductive resistance. The tests and analysis were conducted at a total of 18 locations where the total output power P

_{total}(P

_{out}

_{1}+ P

_{out}

_{2}) was less than 1000 W, which were defined as operation points. In the Section 3.4, Section 3.5, Section 3.6, Section 4.2, and Section 4.3, the numbers indicated in Figure 8 are used to denote the operation points.

#### 3.4. Analysis of Steady Operation

_{out}

_{2}was maintained constant and P

_{out}

_{1}was changed (operation points #01, #02, #03, #04, #05 and #06) and when P

_{out}

_{1}was maintained constant and P

_{out2}was changed (operation points #01, #07, #12 and #16).

_{txs}and I

_{txs}), the current from the transformer to the diode bridge on the V

_{out}

_{1}-side circuit (I

_{recA}and I

_{recB}), the current of L

_{out}

_{1}(I

_{Lout}

_{1}), the return current of the V

_{out}

_{1}-side circuit (I

_{ret}

_{1}), the currents of the series resonant filters (I

_{srA}and I

_{srB}), the current of L

_{out}

_{2}(I

_{Lout}

_{2}), the return current of the V

_{out}

_{2}-side circuit (I

_{ret}

_{2}) and the circulating current (I

_{cir}) that flowed between the GND of both outputs. In Table 4, “+” represents the positive direction, “−” denotes the negative direction and “0” is the condition of no voltage applied or no current flowing.

_{txs}and each current at operation points #04 and #12. The both waveforms of #04 and #12 are divided into 8 modes based on the definition of Table 4, respectively. The operation modes 3, 6 and 9 were not used at operation point #04 and the modes 4, 5 and 8 were not used at #12 as shown in Table 5. Therefore, it is difficult to explain the circuit operation by the 11 operation modes. However, by focusing on the charging condition of L

_{out}

_{1}, the 11 operation modes could be categorized into three groups (A, B and C). The changes in D

_{tx}and f

_{tx}caused by the changes in the operation points can be explained by these three operation modes.

- Group A: L
_{out}_{1}is charged (modes 1 to 5)

_{txs}is positive. As an example, Figure 11a presents the current path in mode 2. The transformer voltage works as the voltage source and L

_{out}

_{1}is charged by the following path: Transformer → D11 → Z

_{sm}

_{1}→ D14 → Transformer.

- Group B: L
_{out}_{1}discharges (modes 6 to 10)

_{txs}is zero and I

_{ret}

_{1}is flowing. As an example, the current path in mode 7 is illustrated in Figure 11b. When L

_{out}

_{1}is discharged, its discharge current returns along the following path: Z

_{sm}

_{1}→ D14 → Transformer → D11 →Z

_{sm}

_{1}.

- Group C: The charge/discharge of L
_{out}_{1}depends on the resonant filter voltage (mode 10)

_{ret}

_{1}and I

_{recB}are zero. The return current from Z

_{sm}

_{1}becomes a circulating current (I

_{cir}) and moves around the return current of the V

_{out}

_{2}side (I

_{ret}

_{2}). This circulating current I

_{cir}flows because the GND of the V

_{out}

_{1}-side and V

_{out}

_{2}-side circuits are common and the return path of the V

_{out}

_{2}-side circuit contains Z

_{srA}or Z

_{srB}. The circulating current of this mode flows according to the state of Z

_{srA}and Z

_{srB}. The current path involved in L

_{out}

_{1}is Z

_{sm}

_{1}→ D22 →Z

_{srA}→ D11 →Z

_{sm}

_{1}. When the both-end voltage of Z

_{srA}(V

_{srA}) exhibits the relationship of V

_{srA}> V

_{out1}, L

_{out}

_{1}is charged by Z

_{srA}and when V

_{srA}< V

_{out}

_{1}, L

_{out}

_{1}discharges.

_{out}

_{2}was constant and P

_{out}

_{1}changed (Figure 12a), the time occupied by mode A increased (D

_{tx}increased) and f

_{tx}decreased (T

_{tx}increased) as P

_{out}

_{1}increased. The increase in D

_{tx}was caused by the increase in P

_{out}

_{1}and the decrease in f

_{tx}occurred to prevent an increase in the power supply to the V

_{out}

_{2}-side circuit caused by the increase in D

_{tx}. However, when P

_{out}

_{1}was constant and P

_{out}

_{2}changed (Figure 12b), P

_{out}

_{2}increased as T

_{tx}decreased (f

_{tx}increased) but few changes occurred in the percentages of the three operation modes (changes in D

_{tx}), regardless of the changes in P

_{out}

_{2}. This indicates that the impedance change of the V

_{out}

_{2}-side circuit caused by the frequency change played a dominant role in the changes in P

_{out}

_{2}.

#### 3.5. Comparative Evaluation of Simulation and Measured Results

_{txp}and V

_{txs}), the currents of the primary and secondary sides of the transformer (I

_{txp}and I

_{txs}), the both-end voltages of D11 and D12 (V

_{d}

_{11}and V

_{d}

_{12}), the L

_{out}

_{1}current and output current (I

_{Lout}

_{1}and I

_{out}

_{1}), the series resonant filter currents (I

_{srA}and I

_{srB}), the series resonant filter voltages (V

_{srA}and V

_{srB}), the both-end voltages of D21 and D22 (V

_{d}

_{21}and V

_{d}

_{22}), the L

_{out}

_{2}current and output current (I

_{Lout}

_{2}and I

_{out}

_{2}) and the circulating current (I

_{cir}). According to Figure 13, the measured and simulation waveforms of #01, #06 and #16 were all very close, which confirms that the verification circuit operated as designed. The errors in D

_{tx}and f

_{tx}, the voltage surge that only appeared in the measured waveforms and the ringing resulting from it were all caused by wiring resistance, parasitic inductance and floating capacitance, which were not included in the simulation.

_{tx}and P

_{out}

_{1}and f

_{tx}and P

_{out}

_{2}, respectively, in steady operation for the measurement and simulation. In addition, the difference between the experimental results and the simulation results for Figure 14 and Figure 15 are depicted in Figure 16. Figure 14, Figure 15 and Figure 16 indicate the experimental tests are operated by larger D

_{tx}and lower f

_{tx}than the simulation tests under all load conditions. The reason for the larger D

_{tx}is that D

_{tx}compensates for V

_{out}

_{1}decreased by the conduction losses of parasitic resistance in the actual circuit and the reason for the lower f

_{tx}is that f

_{tx}controls increasing V

_{out}

_{2}with increasing D

_{tx}. Although these errors appeared, it can be observed that the values of D

_{tx}and f

_{tx}at all operation points in steady operation were close to the simulation results. Therefore, the verification circuit also operated as per the simulation analysis at other operation points that are not shown in the waveforms of Figure 13. This is a further demonstration of the efficacy of the proposed control method.

#### 3.6. Dynamic Characteristics

_{out}

_{2}was maintained constant at 140 W and P

_{out}

_{1}was switched between 285 W and 568 W (#02 and #04 were switched) and when P

_{out}

_{1}was maintained constant at 286 W and P

_{out}

_{2}was switched between 270 W and 393 W (#08 and #13 were switched), respectively. Under any condition of Figure 17 and Figure 18, within 8 ms after the output power was switched, both of the output voltages were adjusted to their respective values prior to the switch. In the measured waveforms of Figure 17, an overshoot with a peak value of around 2 V appeared in both output voltages V

_{out}

_{1}and V

_{out}

_{2}and an error of approximately 0.5 V occurred in the steady value of V

_{out}

_{1}in the measured waveform of Figure 18. However, overall, the measured and simulation waveforms were very close, confirming that the dynamic characteristics of the proposed control method were valid.

## 4. Evaluation of Efficiency and Losses

#### 4.1. Measurement Method

_{in}, P

_{out}

_{1}and P

_{out}

_{2}) was measured with a WT1800 power analyzer. Furthermore, the voltage and current of the transformer primary side (V

_{txp}, I

_{txp}), the voltage and current of the transformer secondary side (V

_{txs}, I

_{txs}) and the voltage and current of the resonant filter of each series (V

_{srA}, V

_{srB}, I

_{srA}, I

_{srB}) were measured using the instruments listed in Table 2. The points of measurement are illustrated in Figure 19.

_{txp}), power of the secondary side of the transformer (P

_{txs}) and power of the resonant filters (P

_{srA}and P

_{srB}) were calculated using the following equation:

#### 4.2. Efficiency Characteristics

_{out}

_{1}on the x-axis. The lowest efficiency of 68.3% was registered at point #16, where P

_{out}

_{1}was the minimum and P

_{out}

_{2}was the maximum. Meanwhile, the maximum efficiency was 88.9% at point #06, where P

_{out}

_{1}was the maximum and P

_{out}

_{2}was the minimum. When P

_{out}

_{2}was constant, the efficiency increased along with P

_{out}

_{1}, regardless of the value of P

_{out}

_{2}, indicating that the load losses caused by P

_{out}

_{2}and other fixed losses were larger than the load losses related to P

_{out}

_{1}. However, when P

_{out}

_{1}was constant, the overall efficiency decreased as P

_{out}

_{2}increased, regardless of the value of P

_{out}

_{1}. This indicates that the load losses related to P

_{out}

_{2}were larger than those caused by P

_{out}

_{1}and other fixed losses. Therefore, the load losses of P

_{out}

_{2}had a significant impact on the efficiency of this circuit.

#### 4.3. Loss Analysis

_{out}

_{1}to the total output power (P

_{out}

_{1}+ P

_{out}

_{2}) was the maximum (#06), when the ratio of P

_{out}

_{2}was the maximum (#16) and under intermediate conditions (#10). For the power at each part obtained by the measurement and calculation, the losses at the inverter (W

_{inv}), transformer (W

_{tx}), series resonant filter (W

_{sr}) and rectifier circuit (W

_{rec}), as well as the total loss (W

_{total}), were calculated using the equation shown in Table 6. The results are illustrated in Figure 21. The left axis indicates the losses and the right axis represents the ratio of P

_{out}

_{2}to the total output power.

_{total}values at the operation points were 144 W (#06), 198 W (#10) and 360 W (#16), whereas the ratios of P

_{out}

_{2}were 14.4% (#06), 32.5% (#10) and 76.7% (#16). Therefore, W

_{total}increased as the ratio of P

_{out}

_{2}increased. Figure 15 demonstrates that, as the ratio of P

_{out}

_{2}increased, f

_{tx}also increased and, simultaneously, the impedance of the V

_{out}

_{2}side decreased and the value of the filter current increased. As a result, the currents of the inverter, transformer and rectifier circuit increased, as did the conduction losses of each part. Moreover, the switching losses of the inverter and rectifier circuit increased, as did the core losses of the transformer and inductor. Therefore, as f

_{tx}increased, the losses of all parts increased; however, the fact that the increase ratio of W

_{sr}and W

_{rec}was larger than that of W

_{inv}and W

_{tx}and the total output power decreased as the ratio of P

_{out}

_{2}increased, indicates that there was little change in W

_{inv}and W

_{tx}, whereas W

_{sr}and W

_{rec}increased at the three operation points, as illustrated in Figure 21.

_{inv}and W

_{tx}at #06 (which exhibited the highest efficiency) accounted for more than half of W

_{total}, it is possible to increase the maximum efficiency by reducing W

_{inv}and W

_{tx}. It is necessary to select switching devices that suit the operation specifications to reduce W

_{inv}, whereas a core with low loss should be selected and the core structure needs to be optimized to reduce W

_{tx}. However, as the efficiency was the lowest when the ratio of P

_{out}

_{2}was the maximum (#16), W

_{sr}and W

_{rec}, which were produced when the current of the V

_{out}

_{2}-side circuit increased, limited the efficiency of the proposed circuit. Therefore, reducing these two values can effectively improve the overall efficiency of the circuit. Decreasing the peak value of the resonant filter current has been suggested as a possible means of reducing the Q value of the series resonant filter but decreasing the Q value means decreasing the sensitivity of the impedance changes to the frequency changes. In this case, it will be necessary to expand the operating frequency range to offset the amount of impedance change. However, if the range is expanded to the high-frequency side, an increased loss will be caused by the higher frequencies, as mentioned previously. Furthermore, if it is expanded to the low-frequency side, the problem of a volume increase in the core of the transformer and inductor will occur. Therefore, it is necessary to determine the optimal conditions.

## 5. Conclusions

_{out}

_{1}= 461 W, P

_{out}

_{2}= 576 W). The dynamic characteristics results show that when switching each output power, it recovered to a steady state within 8 ms after the switching of the operation point. The circuit behaviors at the different load conditions are analyzed by the simulation of the ideal circuit and the simulation waveforms were close to the experimental waveforms. These results demonstrated the validity of the proposed control method.

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 5.**Experimental circuit diagram and setup: (

**a**) Main circuit diagram, (

**b**) Main circuit with control circuit; (

**c**) Main circuit without control circuit.

**Figure 11.**Current path of experimental circuit in each operation mode (the red line indicates the path related to L

_{out}

_{1}): (

**a**) Mode 2; (

**b**) Mode 7; (

**c**) Mode 10.

**Figure 12.**Occupied time and frequency of three operation modes: (

**a**) P

_{out}

_{1}changes from 154 W to 853 W (P

_{out}

_{2}= 142 W); (

**b**) P

_{out}

_{2}changes from 140 W to 581 W (P

_{out}

_{2}= 154 W).

**Figure 14.**Results of D

_{tx}for each measurement point: (

**a**) Experimental results; (

**b**) Simulation results.

**Figure 15.**Results of f

_{tx}for each measurement point: (

**a**) Experimental results; (

**b**) Simulation results.

**Figure 16.**Results of subtract the simulation results from the experimental results for each measurement point: (

**a**) results of D

_{tx}; (

**b**) results of f

_{tx}.

**Figure 17.**Results of P

_{out}

_{1}dynamic response test when P

_{out}

_{2}= 140 W: (

**a**) Experimental results; (

**b**) Simulation results.

**Figure 18.**Results of P

_{out}

_{2}dynamic response test when P

_{out}

_{1}= 286 W: (

**a**) Experimental results; (

**b**) Simulation results.

Parameter | Value |
---|---|

P_{out}_{1} + P_{out}_{2} (MAX) | 1 kW |

P_{out}_{2} (MAX) | 500 W |

V_{in} | 300 V |

V_{out}_{1} | 48 V |

V_{out}_{2} | 12 V |

f_{swmin} | 50 kHz |

f_{swMAX} | 100 kHz |

FPGA | XC7K70T-1FBG484C |

f_{CLK} (T_{CLK}) | 200 MHz (5 ns) |

K_{1} | 2.5 |

K_{2} | 0.5 |

τ_{1} | 3 μs |

τ_{2} | 8 μs |

C_{in} | 330 μF |

S1, S2, S3, S4 | SCT3030AL (ROHM) |

D11, D12, D13, D14, D21, D22, D23, D24 | FFSH4065A (ON Semiconductor) |

Transformer turn ratio | N1:N2 = 20:5 |

L_{sr} | 4.5 μH |

C_{sr} | 560 nF |

L_{out}_{1} | 7.3 μH |

L_{out}_{2} | 7.0 μH |

C_{out}_{1} | 44 μF |

C_{out}_{2} | 188 μF |

f_{0} | 100.3 kHz |

Instrument | Model Number |
---|---|

Oscilloscope | HDO6104A-MS (TELEDYNE) |

Voltage differential probe | 700924 (YOKOGAWA) |

Current probe (<30 A) | TCP312A (Tektronix) |

Current probe (>30 A) | TCP303 (Tektronix) |

Deskew calibration source | DCS025 (TELEDYNE) |

Parameter | Value |
---|---|

V_{in} | 300 V |

V_{out}_{1} | 48 V |

V_{out}_{2} | 12 V |

f_{swmin} | 50 kHz |

f_{swMAX} | 100 kHz |

f_{CLK} (T_{CLK}) | 200 MHz (5 ns) |

K_{1} | 2.5 |

K_{2} | 0.5 |

τ_{1} | 3 μs |

τ_{2} | 8 μs |

C_{in} | 330 μF |

S1, S2, S3, S4 | Ideal devices |

D11, D12, D13, D14, D21, D22, D23, D24 | Ideal devices |

Transformer turn ratio | N1:N2 = 20:5 |

L_{sr} | 4.5 μH |

C_{sr} | 560 nF |

L_{out}_{1} | 7.3 μH |

L_{out}_{2} | 7.0 μH |

C_{out}_{1} | 44 μF |

C_{out}_{2} | 188 μF |

Voltage/Current | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
---|---|---|---|---|---|---|---|---|---|---|---|

V_{txs} | + | + | + | + | + | 0 | 0 | 0 | 0 | 0 | 0 |

I_{txs} | + | + | + | + | + | + | + | + | − | − | − |

I_{recA} | + | + | + | + | + | + | + | + | + | + | + |

I_{recB} | − | − | − | − | − | − | − | − | − | − | 0 |

I_{Lout}_{1} | + | + | + | + | + | + | + | + | + | + | + |

I_{ret}_{1} | + | + | + | + | + | + | + | + | + | + | 0 |

I_{srA} | + | + | + | + | − | + | − | − | − | − | − |

I_{srB} | − | − | + | + | + | + | + | + | + | + | + |

I_{Lout}_{2} | + | + | + | + | + | + | + | + | + | + | + |

I_{ret}_{2} | + | + | + | 0 | + | + | + | + | + | + | + |

I_{cir} | − | + | + | + | + | + | + | − | + | − | − |

Operation Point | Operation Mode | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|

1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | |

#01 | ○ | ○ | ○ | ○ | ○ | ||||||

#02 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ||||

#03 | ○ | ○ | ○ | ○ | ○ | ○ | |||||

#04 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | |||

#05 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | |||

#06 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | |||

#07 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ||||

#12 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | |||

#16 | ○ | ○ | ○ | ○ | ○ | ○ | ○ |

Part | Symbol | Equation |
---|---|---|

Total loss | W_{total} | P_{in} − (P_{out}_{1} + P_{out}_{2}) |

Inverter loss | W_{inv} | P_{in} − P_{txp} |

Transformer loss | W_{tx} | P_{txp} − P_{txs} |

Resonant filter loss | W_{sr} | P_{r}_{1} + P_{r}_{2} |

Rectifier circuit loss | W_{rec} | W_{total} − (W_{inv} + W_{tx} + W_{sr}) |

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## Share and Cite

**MDPI and ACS Style**

Matsushita, Y.; Noguchi, T.; Shimizu, K.; Taguchi, N.; Ishii, M.
Control of Dual-Output DC/DC Converters Using Duty Cycle and Frequency. *World Electr. Veh. J.* **2020**, *11*, 72.
https://doi.org/10.3390/wevj11040072

**AMA Style**

Matsushita Y, Noguchi T, Shimizu K, Taguchi N, Ishii M.
Control of Dual-Output DC/DC Converters Using Duty Cycle and Frequency. *World Electric Vehicle Journal*. 2020; 11(4):72.
https://doi.org/10.3390/wevj11040072

**Chicago/Turabian Style**

Matsushita, Yoshinori, Toshihiko Noguchi, Kazuki Shimizu, Noritaka Taguchi, and Makoto Ishii.
2020. "Control of Dual-Output DC/DC Converters Using Duty Cycle and Frequency" *World Electric Vehicle Journal* 11, no. 4: 72.
https://doi.org/10.3390/wevj11040072