Power Factor Adaptive DPWM Control Strategy for T-Type Three-Level Inverters

Abstract

With the widespread application of multilevel inverters, device losses have become a critical area of research. A key limitation of conventional three-level discontinuous pulse width modulation (DPWM) strategies is their inability to maintain switching device clamping during the peak intervals of the load current, especially under varying load power factor conditions, thereby reducing switching losses. This paper proposes an improved three-level power factor adaptive DPWM (PFA-DPWM) strategy that minimizes switching losses by clamping the power devices during the one-third fundamental period of maximum load current. First, a unified mathematical model of DPWM strategies is established. Theoretical analysis demonstrates that phase disposition (PD) carrier modulation for three-level inverter exhibits superior line voltage harmonic characteristics. Based on this, a theoretical comparison of switching losses and harmonic distortion for various DPWM schemes is conducted. The proposed PFA-DPWM control strategy has the minimum switching loss without compromising harmonic performance. The efficacy and validity of the proposed strategy are confirmed by comprehensive simulation and experimental results.

1. Introduction

The accelerated proliferation of renewable energy, particularly wind and solar photovoltaics, has resulted in a substantial increase in their global installed capacity. Consequently, multilevel converters have become a prominent research topic owing to their advantages, particularly low harmonic distortion in the output voltage and reduced voltage stress on switching devices [1,2,3]. However, the issue of losses in power electronic switching devices has become increasingly significant, constraining the trend toward modular and lightweight designs for power electronic systems. Therefore, optimizing PWM control strategies to improve system efficiency, without altering the hardware circuit, has emerged as a key approach for the efficiency optimization of power electronic devices.

The PWM control strategies for multilevel inverters primarily include sinusoidal pulse-width modulation (SPWM) [4], space vector pulse-width modulation (SVPWM) [5,6], and discontinuous pulse-width modulation (DPWM). Among these, the three-level DPWM strategy can keep the switching devices inactive for one-third of a fundamental period, thereby reducing switching losses. This strategy can effectively improve system efficiency.

The research in refs. [7,8,9] investigates the zero-sequence component injection methods for various two-level DPWM strategies, derives the intrinsic relationship between two-level continuous and discontinuous PWM, and establishes a unified modulation function including SPWM, SVPWM, and various DPWM schemes. In the three-level inverter circuit, the neutral-point potential is regulated using medium and small vectors. However, conventional DPWM strategies exhibit challenges in maintaining neutral-point balance, particularly at a high modulation index. To address this issue, a DPWM strategy based on carrier common mode voltage suppression is proposed to solve the influence of clamping mode on neutral-point current [10]. A novel suppressed common-mode voltage DPWM (SCMV-DPWM) strategy is proposed, which achieves neutral-point (NP) voltage balance by the active regulation of the injected zero-sequence voltage. The control strategy is derived from a NP current model that links the zero-sequence voltage to the resulting NP current, thereby enabling precise voltage regulation in each switching cycle [11]. In the case of increasing the clamping state “0”, the clamping state with the minimum output current ripple is selected for optimal distribution by averaging the current vector amplitude, thereby enhancing the quality of the output current [12]. Traditional DPWM strategies are characterized by a fixed clamping interval, which leads to low-order harmonics in the output current and suboptimal neutral-point voltage balancing performance. A carrier-based DPWM (CB-DPWM) method that employs a variable clamping interval is proposed to concurrently suppress low-order harmonics and enhance the NP voltage balancing capability [13]. In ref. [14], taking the three-phase Vienna rectifier as an example, the common-mode voltage characteristics of different DPWM types are analyzed, and a reverse carrier modulation method to suppress the common-mode voltage is proposed. A dynamic space vector DPWM (DSV-DPWM) method is proposed in ref. [15] to solve the problem of AC input current distortion caused by the unbalanced neutral voltage of the three-level converter. By optimizing the modulation strategy, the vector deviation is eliminated, and the current harmonics are effectively reduced. A method is proposed in ref. [16] to select the operating region based on the phase angle of the reference signal and superimpose the common-mode signal on the reference signal to reduce both the output voltage THD and switching losses. A hybrid DPWM scheme was proposed to achieve neutral-point voltage self-balancing and enhanced power density through a synergistic combination of variable switching frequency and modulation mode selection [17,18]. Modulation methodologies for Cascaded H-Bridge Multilevel Inverters are implemented to enhance power conversion efficiency and harmonic performance in output voltages [19,20]. Furthermore, an optimized DPWM method was proposed in ref. [21], providing deeper insight into the relationship between common-mode voltage and leakage current. The common-mode voltage characteristics of space vectors under different NP conditions are analyzed, and the switching state sequence is optimized to minimize the common-mode voltage to mitigate leakage current. An improved DPWM strategy is proposed to concurrently balance NP voltage, suppress common-mode resonant current, and reduce switching losses. The strategy partitions the 60° DPWM1 clamping interval into three sub-intervals, shortening the net clamping duration to mitigate NP voltage deviations and simplify control. Predefined NP voltage limits the control trade-off between maintaining NP voltage balance and suppressing common-mode current. An offset voltage is then injected to modulate the clamping states, ultimately satisfying all control objectives [22]. The research in refs. [23,24,25,26] comprehensively analyzes the voltage harmonic characteristics and switching losses of various PWM strategies for three-phase inverters under different modulation indices, summarizing the respective advantages, disadvantages, and suitable application scenarios for the strategies.

Conventional DPWM control strategies primarily rely on zero-sequence component injection to transition among different modulation strategies. However, the injected zero-sequence component is derived from the modulation voltage signal, without considering the impact of load current phase on system performance. Specifically, the switching losses of DPWM control strategies exhibit a positive correlation with the instantaneous load current. Consequently, to achieve minimum switching losses, it is imperative that the device clamping interval during the one-third of the fundamental period coincides with the peak absolute load current.

Conventional three-level DPWM strategies fail to track real-time variations in the load power factor (i.e., the current phase angle). This paper proposes a novel three-level power factor adaptive DPWM (PFA-DPWM) strategy to minimize switching losses. The proposed strategy is developed based on an analysis of the unified explicit modulation function for three-level PWM and a load power factor detection model. Furthermore, a harmonic analysis of different three-level carrier-based modulation schemes, particularly phase disposition (PD), phase opposition disposition (POD), and alternative phase opposition disposition (APOD), is conducted. The results indicate that the PD carrier modulation yields superior voltage harmonic characteristics. Finally, a theoretical analysis compares the harmonic performance of the PFA-DPWM strategy with modulation strategies. The simulation and experimental results proposed to verify the practical efficacy of the proposed PFA-DPWM strategy.

2. Three-Level PFA-DPWM Strategy

Taking the T-type three-level inverter as a representative topology, this study derives the intrinsic relationship between various three-level DPWM strategies and the zero-sequence component. Subsequently, the mathematical model of the PFA-DPWM strategy is established.

2.1. Basic Principle of Three-Level DPWM

Compared to the NPC inverter, the power loss of the T-type inverter is lower [27]; therefore, this study utilizes a T-type three-level inverter topology, illustrated in Figure 1, which is augmented with a fourth bridge leg (S_f1, S_f2) to achieve precise neutral-point voltage control and enhance load imbalance performance. The operational principle of the inverter is analyzed by examining a phase x (where x ∈ {a, b, c}), and the midpoint of the DC-link capacitors, denoted as “O”, serves as the zero-voltage reference potential. A fundamental operating constraint of the T-type topology dictates that the upper and lower bridge switches, S_x1 and S_x4, cannot conduct simultaneously. Furthermore, the switching states of the device pairs S_x1, S_x3 and S_x2, S_x4 are complementary. Consequently, three distinct voltage values u_dc/2, 0, and −u_dc/2 are available at the output of the T-type three-level converter, which correspond to three states (“P”, “O”, and “N”).

The fundamental space vector diagram for a three-level inverter is presented in Figure 2a. The diagram is partitioned into six primary sectors and comprises 27 distinct voltage vectors, each of which represents an available switching state. Conventional three-level space vector modulation synthesizes the reference voltage vector by applying a combination of the three nearest adjacent vectors. Of particular note are the small voltage vectors, each of which has two redundant switching states: a P-type and an N-type.

To reduce switching losses, the DPWM strategy operates by clamping a phase leg to either the positive or negative DC bus during a specific interval of the fundamental period. This action effectively reduces the number of switching transitions per fundamental period, thereby transforming the conventional seven-segment switching pattern of SVPWM into a five-segment one. In this process, the selection of the appropriate redundant small vector is determined by the clamped-phase state. For instance, to synthesize a reference vector located in sub-sector 5 of Sector I, phase-a is clamped to P-level, and the reference is synthesized using the three nearest voltage vectors. This principle is extended to remaining sectors, with the resulting complete vector distribution illustrated in Figure 2b.

2.2. Mathematical Model of Traditional Three-Level DPWM Strategy

Conventional DPWM strategies include DPWM0, DPWM1, DPWM2, DPWM-Max, and DPWM-Min, etc. This paper establishes a unified mathematical model for a variety of three-level PWM schemes by zero-sequence component injection. This approach avoids the complex coordinate transformations, sector identification, and vector dwell-time calculations inherent to SVPWM, thereby facilitating straightforward digital implementation.

The three-phase output voltage is expressed as

$$\left\{\begin{array}{l}{u}_{\mathrm{a}}=U_{\mathrm{m}}\sin \omega t\\ u_{\mathrm{b}}=U_{\mathrm{m}}\sin \left(\omega t-2\mathsf{\pi }/3\right)\\ u_{\mathrm{c}}=U_{\mathrm{m}}\sin \left(\omega t-4\mathsf{\pi }/3\right)\end{array}\right.$$

(1)

where U_m = 2M*u_dc/3, M is the modulation index, and u_dc is the DC bus voltage.

According to the intrinsic relationships among three-level PWM control schemes, a unified mathematical model encompassing various continuous and discontinuous strategies can be formulated through the appropriate injection of a zero-sequence component. This model is expressed as

$$\left\{\begin{array}{l}{u}_{\mathrm{ma}}^{*}=u_{\mathrm{a}}+u_{\mathrm{z}}\\ u_{\mathrm{mb}}^{*}=u_{\mathrm{b}}+u_{\mathrm{z}}\\ u_{\mathrm{mc}}^{*}=u_{\mathrm{c}}+u_{\mathrm{z}}\end{array}\right.$$

(2)

$$\left\{\begin{array}{l}{u}_{\mathrm{z}}=(2k-1)-k{u}_{\max }-(1-k)u_{\min }\\ u_{\max }=\max \left\{u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}}\right\}\\ u_{\min }=\min \left\{u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}}\right\}\end{array}\right.$$

(3)

where $u_{\mathrm{ma}}^{*}$, $u_{\mathrm{mb}}^{*}$ and $u_{\mathrm{mc}}^{*}$ denote the modulation signals of three-phase voltages, u_z is the zero-sequence component, k ∈ [0, 1] is the splitting ratio for the different types of zero vectors, and u_max and u_min are the maximum and minimum values of three-phase voltage.

In the abc coordinate system, the three-phase sinusoidal modulating signals (u_a, u_b, and u_c), are combined with an injected zero-sequence component u_z. By varying the parameter k, the allocation of action time for the zero vectors is adjusted, which in turn determines the specific modulation strategy for each modulation period. When k = 1, the DPWM-Max control mode is realized, and only the zero vector (PPP) is used. When k = 0, the DPWM-Min control mode is realized, and only the zero vector (NNN) is used. Furthermore, by alternating the value of k between 0 and 1 at every 60° sector boundary, the DPWM0~2 control mode can be realized. Consequently, the mathematical expression for the zero-sequence component in conventional DPWM strategies can be unified as follows:

$$u_z=\left\{\begin{array}{ll}\left\{\begin{array}{cc}1-u_{\max },& \mathrm{II},\mathrm{IV},\mathrm{VI}\mathit{Sector}\hfill \\ -1-u_{\min },& \mathrm{I},\mathrm{III},\mathrm{V}\mathit{Sector}\hfill \end{array}\right.& \hfill 〈\mathrm{DPWM}0〉\\ \left\{\begin{array}{cc}1-u_{\max },& \mathit{if}\left|u_{\max }\right|>\left|u_{\min }\right|\hfill \\ -1-u_{\min },& \mathit{if}\left|u_{\max }\right|<\left|u_{\min }\right|\hfill \end{array}\right.& \hfill 〈\mathrm{DPWM}1〉\\ \left\{\begin{array}{cc}1-u_{\max },& \mathrm{I},\mathrm{III},\mathrm{V}\mathit{Sector}\hfill \\ -1-u_{\min },& \mathrm{II},\mathrm{IV},\mathrm{VI}\mathit{Sector}\hfill \end{array}\right.& \hfill 〈\mathrm{DPWM}2〉\\ 1-u_{\max }& \hfill 〈\text{DPWM-Max}〉\\ -1-u_{\min }& \hfill 〈\text{DPWM-Min}〉\end{array}\right.$$

(4)

2.3. Mathematical Model of Three-Level PFA-DPWM Strategy

A method for detecting the instantaneous load power factor was previously presented by the authors in ref. [28] and will not be reiterated here. DPWM strategies mitigate switching losses by alternately remaining the power devices inactive for one-third of the fundamental period, an interval during which no switching occurs.

By utilizing the modulating voltage, phase-shifted by the power factor angle, as the condition for configuring the zero-sequence component, a mathematical model for the proposed PFA-DPWM strategy can be derived as follows

$$\left\{\begin{array}{l}{u}_{\mathrm{a}}^{\prime }(\phi )=u_{\mathrm{a}}(\omega t-\phi )\\ u_{\mathrm{b}}^{\prime }(\phi )=u_{\mathrm{b}}(\omega t-\phi )\\ u_{\mathrm{c}}^{\prime }(\phi )=u_{\mathrm{c}}(\omega t-\phi )\end{array}\right.$$

(5)

where $u_{\mathrm{a}}$, $u_{\mathrm{b}}$, and $u_{\mathrm{c}}$ denote the original phase voltages. $u_{\mathrm{a}}^{\prime }(\phi )$, $u_{\mathrm{b}}^{\prime }(\phi )$ and $u_{\mathrm{c}}^{\prime }(\phi )$ denote the phase voltages after being phase-shifted by the load power factor angle φ.

The maximum and minimum values of the original and phase-shifted voltages are shown as follows:

$$\left\{\begin{array}{l}{u}_{\max }=\max \left\{u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}}\right\}\\ u_{\min }=\min \left\{u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}}\right\}\\ u_{\max }^{\prime }(\phi )=\max \left\{u_{\mathrm{a}}^{\prime }(\phi ),u_{\mathrm{b}}^{\prime }(\phi ),u_{\mathrm{c}}^{\prime }(\phi )\right\}\\ u_{\min }^{\prime }(\phi )=\min \left\{u_{\mathrm{a}}^{\prime }(\phi ),u_{\mathrm{b}}^{\prime }(\phi ),u_{\mathrm{c}}^{\prime }(\phi )\right\}\end{array}\right.$$

(6)

Therefore, the zero-sequence voltage function of three-level PFA-DPWM can be expressed as

$$u_{\mathrm{mz}}(\phi )=\left\{\begin{array}{ll}-1-u_{\min },& if\left|u_{\max }^{\prime }(\phi )\right|<\left|u_{\min }^{\prime }(\phi )\right|\\ 1-u_{\max },& if\left|u_{\max }^{\prime }(\phi )\right|>\left|u_{\min }^{\prime }(\phi )\right|\end{array}\right.$$

(7)

$$\left\{\begin{array}{c}{u}_{\mathrm{ma}}^{*}(\phi )=u_{\mathrm{a}}+u_{\mathrm{mz}}(\phi )\\ u_{\mathrm{mb}}^{*}(\phi )=u_{\mathrm{b}}+u_{\mathrm{mz}}(\phi )\\ u_{\mathrm{mc}}^{*}(\phi )=u_{\mathrm{c}}+u_{\mathrm{mz}}(\phi )\end{array}\right.$$

(8)

where $u_{\mathrm{mz}}(\phi )$ is the zero-sequence voltage of the three-level PFA-DPWM. $u_{\mathrm{ma}}^{*}(\phi )$, $u_{\mathrm{ma}}^{*}(\phi )$, and $u_{\mathrm{mc}}^{*}(\phi )$ are the modulation voltages of the three-level PFA-DPWM.

Figure 3 shows the modulation waveforms for various PWM control strategies at a power factor angle of φ = π/12. The PFA-PWM strategy can maintain clamping of the power device during one-third of the fundamental period at maximum load current.

3. Analysis of Different Three-Level Carrier Modulation Schemes

Beyond the fundamental component, the output voltage also contains harmonic components generated during the switching process. Therefore, characterizing the distribution and magnitude of these harmonics is crucial for the selection of a carrier modulation strategy and the design of output filters. This section quantitatively analyzes the harmonic component of the output voltage by applying the double Fourier series method [29].

The carrier modulation schemes can be categorized as either sawtooth or triangular. Given that triangular carriers offer superior harmonic characteristics, the subsequent analysis is confined to modulation schemes that employ them. There are three common triangular carrier-based modulation schemes:

(1)

PD: All carrier signals are mutually in phase.

(2)

POD: The carriers above the zero reference are phase-shifted by 180° relative to those below it.

(3)

APOD: Each carrier is phase-shifted by 180° with respect to its adjacent carriers.

For three-level inverters, the POD and APOD schemes are functionally equivalent. Consequently, they are consolidated into a single analytical category, as illustrated in Figure 4.

To facilitate the analysis, the carrier functions f_c+(x), f_c−(x), and the modulating function f_m(y), are defined as shown in

Table 1. Carrier functions f_c+(x), f_c−(x) and modulating function f_m(y).

	${\mathit{f}}_{\mathbf{c}+}(\mathit{x})$	${\mathit{f}}_{\mathbf{c}-}(\mathit{x})$	${\mathit{f}}_{\mathbf{m}}(\mathit{y})$
PD	$\left\{\begin{array}{ll}{\displaystyle \frac{x}{\mathsf{\pi }}}& 0<x\le \mathsf{\pi }\\ -{\displaystyle \frac{x}{\mathsf{\pi }}}& -\mathsf{\pi }\le x\le 0\end{array}\right.$	$\left\{\begin{array}{ll}-1+{\displaystyle \frac{x}{\mathsf{\pi }}}& 0<x\le \mathsf{\pi }\\ -1-{\displaystyle \frac{x}{\mathsf{\pi }}}& -\mathsf{\pi }\le x\le 0\end{array}\right.$	$M\cos y$
POD/APOD	$\left\{\begin{array}{ll}{\displaystyle \frac{x}{\mathsf{\pi }}}& 0<x\le \mathsf{\pi }\\ -{\displaystyle \frac{x}{\mathsf{\pi }}}& -\mathsf{\pi }\le x\le 0\end{array}\right.$	$\left\{\begin{array}{ll}-{\displaystyle \frac{x}{\mathsf{\pi }}}& 0<x\le \mathsf{\pi }\\ {\displaystyle \frac{x}{\mathsf{\pi }}}& -\mathsf{\pi }\le x\le 0\end{array}\right.$	$M\cos y$

. The phase voltage switching function for the PD modulation scheme f_PD(x, y) is presented in

Table 2. Phase voltage switching function f_PD(x, y) for PD modulation.

${\mathit{f}}_{\mathbf{PD}}(\mathit{x},\mathit{y})$	$-\mathsf{\pi }\le \mathit{x}\le 0$	$0<\mathit{x}\le \mathsf{\pi }$
${\displaystyle \frac{V_{\mathrm{dc}}}{2}}$	$M\cos \mathrm{y}\text{>}-{\displaystyle \frac{x}{\mathsf{\pi }}}$	$M\cos \mathrm{y}\text{>}{\displaystyle \frac{x}{\mathsf{\pi }}}$
0	$-{\displaystyle \frac{x}{\mathsf{\pi }}}\text{>}M\cos \mathrm{y}>-1-{\displaystyle \frac{x}{\mathsf{\pi }}}$	${\displaystyle \frac{x}{\mathsf{\pi }}}\text{>}M\cos \mathrm{y}>-1+{\displaystyle \frac{x}{\mathsf{\pi }}}$
$-{\displaystyle \frac{V_{\mathrm{dc}}}{2}}$	$M\mathrm{cosy}\text{<}-1-{\displaystyle \frac{x}{\mathsf{\pi }}}$	$M\mathrm{cosy}\text{<}-1+{\displaystyle \frac{x}{\mathsf{\pi }}}$

. Similarly, the function for the POD/APOD schemes f_POD/APOD(x, y) is given in

Table 3. Phase voltage switching function f_POD/APOD(x, y) for POD/APOD modulation.

${\mathit{f}}_{\mathbf{POD}/\mathbf{APOD}}(\mathit{x},\mathit{y})$	$-\mathsf{\pi }\le \mathit{x}\le 0$	$0<\mathit{x}\le \mathsf{\pi }$
${\displaystyle \frac{V_{\mathrm{dc}}}{2}}$	$M\cos y\text{>}-{\displaystyle \frac{x}{\mathsf{\pi }}}$	$M\cos y\text{>}{\displaystyle \frac{x}{\mathsf{\pi }}}$
0	$-{\displaystyle \frac{x}{\mathsf{\pi }}}\text{>}M\cos y>{\displaystyle \frac{x}{\mathsf{\pi }}}$	${\displaystyle \frac{x}{\mathsf{\pi }}}\text{>}M\cos y>-{\displaystyle \frac{x}{\mathsf{\pi }}}$
$-{\displaystyle \frac{V_{\mathrm{dc}}}{2}}$	$M\cos y\text{<}{\displaystyle \frac{x}{\mathsf{\pi }}}$	$M\cos y\text{<}-{\displaystyle \frac{x}{\mathsf{\pi }}}$

, where x = ω_ct, y = ω_mt + θ_m [30,31].

The voltage switching function f_POD/APOD(x, y) is a bivariate function. Consequently, it is expressed by a double Fourier series expansion as follows [30]

$$\begin{array}{ll}f(x,y)& ={\displaystyle \frac{A_{00}}{2}}+{\displaystyle \sum _{n=1}^{\infty }\{A_{0n}\cos [n({\omega }_{0}t+{\theta }_0)]}+B_{0n}\sin [n({\omega }_{0}t+{\theta }_0)]\}+\\ & {\displaystyle \sum _{m=1}^{\infty }\{A_{m0}\cos [m({\omega }_{\mathrm{c}}t+{\theta }_{\mathrm{c}})]}+B_{m0}\sin [m({\omega }_{\mathrm{c}}t+{\theta }_{\mathrm{c}})]\}+\\ & {\displaystyle \sum _{m=1}^{\infty }{\displaystyle \sum _{n=\pm 1}^{\pm \infty }\left\{\begin{array}{l}{A}_{mn}\cos [m({\omega }_{\mathrm{c}}t+{\theta }_{\mathrm{c}})+n({\omega }_{0}t+{\theta }_0)\\ +B_{mn}\sin [m({\omega }_{\mathrm{c}}t+{\theta }_{\mathrm{c}})+n({\omega }_{0}t+{\theta }_0)\end{array}\right\}}}\end{array}$$

(9)

where

$$A_{mn}={\displaystyle \frac{1}{{2\mathsf{\pi }}^2}}{\displaystyle {\int }_{-\mathsf{\pi }}^{\mathsf{\pi }}{\displaystyle {\int }_{-\mathsf{\pi }}^{\mathsf{\pi }}f(x,y)}}\cos (mx+ny)dxdy$$

$$B_{mn}={\displaystyle \frac{1}{2{\mathsf{\pi }}^2}}{\displaystyle {\int }_{-\mathsf{\pi }}^{\mathsf{\pi }}{\displaystyle {\int }_{-\mathsf{\pi }}^{\mathsf{\pi }}f(x,y)}}\sin (mx+ny)dxdy$$

By applying the double Fourier series method from (9), the expression for the phase voltage harmonic analysis in the PD modulation can be obtained:

$$\begin{array}{ll}{f}_{\mathrm{PD}}(x,y)& ={\displaystyle \frac{V_{\mathrm{dc}}M\cos ({\omega }_{\mathrm{o}}t+{\theta }_{\mathrm{o}})}{2}}+{\displaystyle \frac{4V_{\mathrm{dc}}}{{\mathsf{\pi }}^2}}{\displaystyle \sum _{m=1}^{\infty }\frac{1}{2m-1}{\displaystyle \sum _{k=1}^{\infty }\frac{J_{2\mathrm{k}-1}[(2m-1)\mathsf{\pi }M]}{2k-1}}}\cos [(2m-1){\omega }_{\mathrm{c}}t]+\\ & {\displaystyle \frac{V_{\mathrm{dc}}}{{\mathsf{\pi }}^2}}{\displaystyle \sum _{m=1}^{\infty }\frac{1}{2m}{\displaystyle \sum _{n=-\infty }^{\infty }{J}_{2\mathrm{n}+1}(2m\mathsf{\pi }M)}}\cos n\mathsf{\pi }\cos [2m{\omega }_{\mathrm{c}}t+(2n+1)({\omega }_{\mathrm{o}}t+{\theta }_{\mathrm{o}})]+\\ & {\displaystyle \frac{4V_{\mathrm{dc}}}{{\mathsf{\pi }}^2}}{\displaystyle \sum _{m=1}^{\infty }\frac{1}{2m-1}{\displaystyle \sum _{\begin{array}{l}n=-\infty \\ (n\ne 0)\end{array}}^{\infty }{\displaystyle \sum _{k=1}^{\infty }\frac{J_{2\mathrm{k}-1}[(2m-1)\mathsf{\pi }M](2k-1)}{(2k-1+2n)(2k-1-2n)}}}}\cos n\mathsf{\pi }\times \cos [(2m-1){\omega }_{\mathrm{c}}t+2n({\omega }_{\mathrm{o}}t+{\theta }_{\mathrm{o}})]\end{array}$$

(10)

Similarly, the expression for the phase voltage harmonic components in the POD/APOD modulation can be obtained:

$$\begin{array}{l}{f}_{\mathrm{POD}/\mathrm{APOD}}(x,y)={\displaystyle \frac{V_{\mathrm{dc}}M\cos ({\omega }_{\mathrm{o}}t+{\theta }_{\mathrm{o}})}{2}}+\\ {\displaystyle \frac{V_{\mathrm{dc}}}{{\mathsf{\pi }}^2}}{\displaystyle \sum _{m=1}^{\infty }\frac{1}{m}{\displaystyle \sum _{\begin{array}{l}\mathrm{n}=-\infty \\ (\mathrm{n}\ne 0)\end{array}}^{\infty }{J}_{2\mathrm{n}+1}(m\mathsf{\pi }M)}}\cos n\mathsf{\pi }\cos [m{\omega }_{\mathrm{c}}t+(2n+1)({\omega }_{\mathrm{o}}t+{\theta }_{\mathrm{o}})]\end{array}$$

(11)

Based on (10) and (11), the harmonic component expression of the line-to-line voltage f_ab(x, y) can be expressed as

$$f_{\mathrm{ab}}(x,y)=f_{\mathrm{a}}(x,y)-f_{\mathrm{b}}(x,y)$$

(12)

For a modulation index of M = 0.8 and a carrier ratio of f_c/f_m = 50, the spectra for the phase-a voltage under the PD and POD/APOD modulation schemes are illustrated in Figure 5. The corresponding line-to-line voltage (ab voltage) spectra are illustrated in Figure 6.

As derived by (10) and visually corroborated by the spectral analyses in Figure 5 and Figure 6, the harmonic components of the PD modulation scheme exhibit the following characteristics:

(1)

The phase voltage contains abundant harmonic components at the carrier frequency. These carrier harmonics are common-mode components and are inherently canceled in the line-to-line voltage.

(2)

Harmonics with even-order sidebands are present around odd multiples of the carrier frequency, and harmonics with odd-order sidebands are present around even multiples of the carrier frequency.

Following a similar procedure, the harmonic characteristics for the POD/APOD modulation schemes can be formulated based on (11), as illustrated in Figure 5 and Figure 6:

(1)

The phase voltage spectrum does not contain odd-order carrier frequency harmonics; only their sideband harmonic components are present. Consequently, the harmonic energy is dispersed among them.

(2)

The odd-order sideband harmonics surrounding even multiples of the carrier frequency are identical to those produced by the PD scheme.

Although the phase voltage THD is nearly identical for both PD and POD/APOD schemes, the line-to-line voltage THD for the PD scheme is significantly lower. This performance difference arises because, in the line-to-line voltage of the POD/APOD schemes, harmonic cancelation is less effective; specifically, only the triplen sideband harmonics around carrier are canceled. As a result, a greater amount of harmonic energy is retained.

Therefore, based on its superior line-to-line voltage harmonic profile, the PD modulation scheme is selected for implementation in this study.

4. Performance Analysis of Three-Level DPWM Strategies

Harmonic distortion and switching loss are critical factors in the selection of a DPWM strategy. This section will, therefore, present a theoretical derivation of these performance metrics for various DPWM strategies to establish the evaluation criteria for an optimal selection.

4.1. Harmonic Distortion

Harmonic distortion is an important parameter for evaluating different PWM control strategies. Assuming the average internal electromotive force (EMF) of the load e_xy, is constant within any given switching period and neglecting load losses, multiple switching states exist for a specific load EMF condition. For instance, when e_xy > 0, there are four possible switching combinations within a single carrier period, as shown in Figure 7.

For the case where 0 > u_x > u_y, the current ripple through the load during the time intervals T₁, T₂, and T₃ can be defined as

$$\left\{\begin{array}{ll}\Delta i_{xy}(t)=-{\displaystyle \frac{e_{xy}}{L_{\mathsf{\sigma }}}}t& \left(0\le t\le T_1\right)\\ \Delta i_{xy}(t)={\displaystyle \frac{V_{\mathrm{dc}}-e_{xy}}{L_{\mathsf{\sigma }}}}(t-T_1)-{\displaystyle \frac{e_{xy}}{L_{\mathsf{\sigma }}}}{T}_1& \left(T_1<t\le T_1+T_2\right)\\ \Delta i_{xy}(t)=-{\displaystyle \frac{e_{xy}}{L_{\mathsf{\sigma }}}}(t-T_1-T_2)+{\displaystyle \frac{V_{\mathrm{dc}}-e_{xy}}{L_{\mathsf{\sigma }}}}{T}_2-{\displaystyle \frac{e_{xy}}{L_{\mathsf{\sigma }}}}{T}_1& \left(T_1+T_2<t\le T_1+T_2+T_3\right)\end{array}\right.$$

(13)

where L_σ is the line-to-line equivalent leakage inductance and e_xy is the average internal electromotive force of the load, x, y ∈ {a, b, c}.

By substituting t = T₁ + T₂ + T₃ = ΔT/2 into (13), the following expression is obtained:

$$\Delta i_{xy}({\displaystyle \frac{\Delta T}{2}})=-{\displaystyle \frac{e_{xy}}{L_{\mathsf{\sigma }}}}{T}_3+{\displaystyle \frac{V_{\mathrm{dc}}-e_{xy}}{L_{\mathsf{\sigma }}}}{T}_2-{\displaystyle \frac{e_{xy}}{L_{\mathsf{\sigma }}}}{T}_1=0$$

(14)

From Equation (14), the following can be derived

$$T_2=(u_x-u_y)\Delta T/2$$

(15)

where $u_x={\displaystyle \frac{e_x}{V_{\mathrm{dc}}}}$, $u_y={\displaystyle \frac{e_y}{V_{\mathrm{dc}}}}$, then $u_x-u_y={\displaystyle \frac{e_{xy}}{V_{\mathrm{dc}}}}$.

Similarly, the expressions of T₁ and T₃ can be obtained:

$$\left\{\begin{array}{l}{T}_1=(1+u_y)\Delta T/2\\ T_3=(-u_x)\Delta T/2\end{array}\right.$$

(16)

The mean square value of the current ripple in ΔT/2 is given by (17)

$$〈{\Delta i_{\mathrm{xy}}}^2〉={\left({\displaystyle \frac{V_{\mathrm{dc}}}{L_{\mathsf{\sigma }}}}\right)}^2{\displaystyle \frac{2}{\Delta T}}\left\{\begin{array}{l}{\displaystyle \underset{0}{\overset{T_1}{\int }}{(u_{\mathrm{y}}-u_{\mathrm{x}})}^2{t}^{2}dt}+{\displaystyle \underset{0}{\overset{T_2}{\int }}[(1+u_{\mathrm{y}}-u_{\mathrm{x}})x+(u_{\mathrm{y}}-u_{\mathrm{x}})T_1{]}^{2}dx+}\\ {\displaystyle \underset{0}{\overset{T_3}{\int }}{[(u_{\mathrm{y}}-u_{\mathrm{x}})x^{\prime }+(1+u_{\mathrm{y}}-u_{\mathrm{x}})T_2+(u_{\mathrm{y}}-u_{\mathrm{x}})T_1]}^{2}d{x}^{\prime }}\end{array}\right\}$$

(17)

where x = t − T₁, x’ = t − T₁ − T₂.

By substituting T₁, T₂, and T₃ into (17), the following expression is obtained:

$$〈{\Delta i_{\mathrm{xy}}}^2〉={\left({\displaystyle \frac{V_{\mathrm{dc}}}{L_{\mathsf{\sigma }}}}\right)}^2{\displaystyle \frac{\Delta T^2}{12}}{(u_{\mathrm{x}}-u_{\mathrm{y}})}^2[{u_{\mathrm{x}}}^2+u_{\mathrm{x}}(1+u_{\mathrm{y}})+{(1+u_{\mathrm{y}})}^2]$$

(18)

Following a similar procedure, the time intervals T₁, T₂, T₃, and the corresponding current ripple for the three switching combinations depicted in Figure 7b–d is derived, with the results summarized in

Table 4. Mean square value of current ripple for various switching state combinations.

Conditions	T1, T2, T3	RMS of Current Ripple
$0>u_x>u_y$	$T_1=(1+u_y)\Delta T/2$ $T_2=(u_x-u_y)\Delta T/2$ $T_3=-u_{\mathrm{x}}\Delta T/2$	$〈\Delta {i_{xy}}^2〉={\left({\displaystyle \frac{V_{\mathrm{dc}}}{L_{\mathsf{\sigma }}}}\right)}^2{\displaystyle \frac{\Delta T^2}{12}}{(u_x-u_y)}^2[{u_x}^2+u_x(1+u_y)+{(1+u_y)}^2]$
$u_x>u_y>0$	$T_1=u_y\Delta T/2$ $T_2=(u_x-u_y)\Delta T/2$ $T_3=(1-u_x)\Delta T/2$	$〈\Delta {i_{\mathrm{x}y}}^2〉={\left({\displaystyle \frac{V_{\mathrm{dc}}}{L_{\mathsf{\sigma }}}}\right)}^2{\displaystyle \frac{\Delta T^2}{12}}{(u_x-u_y)}^2[(u_x-1{)}^2+(u_x-1)u_y+{u_y}^2]$
$\begin{array}{l}{u}_x>0>u_y\\ ,u_x-u_y>1\end{array}$	$T_1=(1+u_y)\Delta T/2$ $T_2=(u_x-u_y-1)\Delta T/2$ $T_3=(1-u_x)\Delta T/2$	$〈\Delta {i_{xy}}^2〉={\left({\displaystyle \frac{V_{\mathrm{dc}}}{L_{\mathsf{\sigma }}}}\right)}^2{\displaystyle \frac{\Delta T^2}{12}}{(-1+u_x-u_y)}^2(1-u_x+{u_x}^2+u_y+u_x{u}_y+{u_y}^2)$
$\begin{array}{l}{u}_{\mathrm{x}}>0>u_{\mathrm{y}}\\ ,u_{\mathrm{x}}-u_{\mathrm{y}}<1\end{array}$	$T_1=u_x\Delta T/2$ $T_2=(1-u_x+u_y)\Delta T/2$ $T_3=-u_y\Delta T/2$	$〈\Delta {i_{xy}}^2〉={\left({\displaystyle \frac{V_{\mathrm{dc}}}{L_{\mathsf{\sigma }}}}\right)}^2{\displaystyle \frac{\Delta T^2}{12}}{(1-u_x+u_y)}^2({u_x}^2+u_x{u}_y+{u_y}^2)$

.

From the above derivations, the harmonic distortion for each modulation strategy can be obtained. For example, the SPWM harmonic distortion is given by (19), and the detailed derivation of (19) is provided in the Appendix A.

$${\mathrm{F}}_{\mathrm{SPWM}}\left(M\right)=\left\{\begin{array}{ll}{\displaystyle \frac{4\mathsf{\pi }-3\sqrt{3}}{4}}{M}^2-{\displaystyle \frac{3+4\sqrt{3}}{2}}{M}^3+{\displaystyle \frac{9\mathsf{\pi }}{8}}{M}^4& \hfill 0<M\le {\displaystyle \frac{\sqrt{3}}{3}}\\ \begin{array}{l}(2+9M^2\left)\arccos \right({\displaystyle \frac{1}{\sqrt{3}M}})+{\displaystyle \frac{-3\sqrt{3}+4\mathsf{\pi }}{4}}{M}^2-\\ {\displaystyle \frac{3+4\sqrt{3}}{2}}{M}^3-({\displaystyle \frac{11}{3}}+4M^2)\sqrt{3M^2-1}+{\displaystyle \frac{9\mathsf{\pi }}{8}}{M}^4\end{array}& \hfill M>{\displaystyle \frac{\sqrt{3}}{3}}\end{array}\right.$$

(19)

The mean square value of the total harmonic current for SVPWM is given by

$${\mathrm{F}}_{\mathrm{SVPWM}}\left(M\right)=\left\{\begin{array}{ll}{\displaystyle \frac{1}{768}}\left(-720+256\sqrt{3}\right)M^3+{\displaystyle \frac{3}{32}}{M}^2\left(-\sqrt{3}+\pi \right)+{\displaystyle \frac{9}{256}}{M}^4\left(-3\sqrt{3}+4\pi \right)& \hfill 0<M<{\displaystyle \frac{\sqrt{3}}{3}}\\ {\displaystyle \frac{\left(792\pi -864ArcCsc\left[\sqrt{3}M\right]\right)M^2}{2304}}+{\displaystyle \frac{\left(-2160+504\sqrt{3}\right)M^3}{2304}}+{\displaystyle \frac{\left(-288\sqrt{3}-384M\sqrt{-1+3M^2}\right)M}{2304}}+& \\ {\displaystyle \frac{\left(-243\sqrt{3}+324\pi \right)M^4}{2304}}+-{\displaystyle \frac{11M\sqrt{-1+3M^2}}{72M}}+{\displaystyle \frac{128\pi -192ArcCsc\left[\sqrt{3}M\right]}{2304}}& \hfill {\displaystyle \frac{\sqrt{3}}{3}}<M<{\displaystyle \frac{2}{3}}\\ \left(-{\displaystyle \frac{3\sqrt{3}}{32}}+{\displaystyle \frac{3\pi }{32}}+{\displaystyle \frac{3}{4}}ArcSec\left[\sqrt{3}M\right]\right)M^2+\left(-{\displaystyle \frac{15}{16}}+{\displaystyle \frac{1}{\sqrt{3}}}\right)M^3+\left(-{\displaystyle \frac{27\sqrt{3}}{256}}+{\displaystyle \frac{9\pi }{64}}\right)M^4& \\ -{\displaystyle \frac{11M\sqrt{-1+3M^2}}{36M}}-{\displaystyle \frac{1}{3}}{M}^2\sqrt{-1+3M^2}+{\displaystyle \frac{1}{6}}ArcSec\left[\sqrt{3}M\right]& \hfill {\displaystyle \frac{2}{3}}<M<1\end{array}\right.$$

(20)

The derivation process for other PWM strategies follows a similar approach. However, the expressions for F(M) are more complex and require mathematical software for their derivation, which is omitted here for the sake of brevity.

The harmonic distortion curves for different PWM strategies are plotted in Figure 8. The harmonic distortion function for the PFA-DPWM (φ = π/12) lies between those of DPWM0/2 and DPWM1. At low modulation indices, its harmonic performance is superior to that of DPWM1, while at high modulation indices, it surpasses DPWM0 and DPWM2.

4.2. Switching Losses

In high-power electronic systems, switching loss is also a critical parameter for evaluating the performance of DPWM strategies, as the device switching loss is proportional to the magnitude of the instantaneous load current. This section derives a mathematical model for the switching loss of a three-level DPWM over half a switching period and conducts a comparative analysis of the switching losses under different modulation strategies. For half a switching period, the PWM switching loss can be uniformly expressed as

$$P_{\mathrm{loss}\left(\mathrm{pwm}\right)}=U_{\mathrm{e}}{I}_{\mathrm{m}}{\displaystyle \frac{1}{\mathsf{\pi }}}{\displaystyle {\int }_{\phi }^{\mathsf{\pi }+\phi }\left|\sin (\theta -\phi )\right|}d\theta$$

(21)

Therefore, the switching loss function of SVPWM can be derived as

$$P_{\mathrm{loss}\left(\mathrm{svpwm}\right)}={\displaystyle \frac{2}{\mathsf{\pi }}}{U}_{\mathrm{e}}{I}_{\mathrm{m}}$$

(22)

The switching loss function of DPWM0 is

$$P_{\mathrm{loss}\left(\mathrm{DPWM}0\right)}(\phi )=U_{\mathrm{e}}{\mathrm{I}}_m{\displaystyle \frac{2}{\mathsf{\pi }}}\left({\displaystyle {\int }_0^{\frac{\mathsf{\pi }}{2}}\left|\sin (\theta -\phi )\right|}d\theta +{\displaystyle {\int }_{\frac{5\mathsf{\pi }}{6}}^{\mathsf{\pi }}\left|\sin (\theta -\phi )\right|d\theta }\right)$$

(23)

The switching loss function of DPWM2 is

$$P_{\mathrm{loss}\left(\mathrm{DPWM}2\right)}(\phi )=U_{\mathrm{e}}{\mathrm{I}}_m{\displaystyle \frac{2}{\mathsf{\pi }}}\left({\displaystyle {\int }_0^{\frac{\mathsf{\pi }}{6}}\left|\sin (\theta -\phi )\right|}d\theta +{\displaystyle {\int }_{\frac{\mathsf{\pi }}{2}}^{\mathsf{\pi }}\left|\sin (\theta -\phi )\right|d\theta }\right)$$

(24)

The calculation for other DPWM strategies is similar, and it is only necessary to consider that different types of DPWM strategies have different switch clamping intervals.

The resulting simplified mathematical model for the three-level PFA-DPWM is

$$P_{\mathrm{loss}(\mathrm{PFA}-\mathrm{DPWM})}(\phi )=\left\{\begin{array}{cc}{P}_{\mathrm{loss}\left(\mathrm{DPWM}2\right)}(\phi )\hfill & (\phi <-{\displaystyle \frac{\mathsf{\pi }}{6}})\\ {\displaystyle \frac{1}{2}}\hfill & (-{\displaystyle \frac{\mathsf{\pi }}{6}}<\phi <{\displaystyle \frac{\mathsf{\pi }}{6}})\\ P_{\mathrm{loss}\left(\mathrm{DPWM}0\right)}(\phi )\hfill & (\phi >{\displaystyle \frac{\mathsf{\pi }}{6}})\end{array}\right.$$

(25)

The proposed three-level PFA-DPWM control strategy adaptively tracks the variation in the load power factor angle φ, ensuring the switching devices are clamped for one-third of the fundamental period, an interval aligned with the peak of the phase current. Theoretical derivation shows that the strategy is equivalent to DPWM2 when φ < −π/6 and to DPWM0 when φ > π/6. In the range of −π/6 < φ < π/6, its operational behavior is contingent upon the load power factor angle. Using the switching loss of SVPWM as a baseline, a normalized loss function is defined in (28). The switching losses for different three-level DPWM strategies are compared in Figure 9.

$$P_{\mathrm{DPWMx}}(\phi )={\displaystyle \frac{P_{\mathrm{loss}\left(\mathrm{DPWMx}\right)}(\phi )}{P_{\mathrm{loss}\left(\mathrm{SVPWM}\right)}}}$$

(26)

As illustrated in Figure 9, the PFA-DPWM strategy is equivalent to DPWM2 for φ < −π/6 and to DPWM0 for φ > π/6, while tracking the load power factor angle in the range of −π/6 < φ < π/6. As a result, the proposed three-level PFA-DPWM strategy effectively constructs the lower envelope of the switching losses among the compared strategies, thereby ensuring near-optimal efficiency across the entire power factor range.

4.3. Loss Model and Efficiency Analysis

The overall losses of an inverter predominantly consist of semiconductor device losses and magnetic component losses. To illustrate, the loss model for the T-type inverter operating under unity power factor conditions while employing the PFA-DPWM strategy.

The three-phase output current can be represented as

$$\left\{\begin{array}{l}{i}_{\mathrm{a}}=I_{\mathrm{m}}\cos \omega t\\ i_{\mathrm{b}}=I_{\mathrm{m}}\cos \left(\omega t-2\mathsf{\pi }/3\right)\\ i_{\mathrm{c}}=I_{\mathrm{m}}\cos \left(\omega t+2\mathsf{\pi }/3\right)\end{array}\right.$$

(27)

Under dual-carrier modulation, the phase leg voltage exhibits two distinct states within each switching period: a non-zero level (positive or negative) and a zero level. This voltage level, in turn, dictates the conduction path of the phase current: for a non-zero voltage, the current is conducted by one of the outer switches, whereas for a zero voltage, it flows through a neutral-point switch and its corresponding anti-parallel diode. Assuming operation under unity power factor, the duty cycles for the non-zero and zero voltage levels are denoted as D_±1 and D₀, respectively:

$$D_{\pm 1}=\left|{\displaystyle \frac{u_{\mathrm{a}}^{\ast }}{U_{\mathrm{M}}}}\right|$$

(28)

$$D_0=1-\left|{\displaystyle \frac{u_{\mathrm{a}}^{\ast }}{U_{\mathrm{M}}}}\right|$$

(29)

The conduction loss for phase A over one complete line-frequency cycle is given by

$$P_{\mathrm{cond}}=f_{\mathrm{g}}{\displaystyle {\int }_0^{1/f_{\mathrm{g}}}\left(v_{\mathrm{CE}1}\cdot D_{\pm 1}+v_{\mathrm{CE}0}\cdot {\mathrm{D}}_0+v_{D0}\cdot D_0\right)\cdot \left|i_{\mathrm{a}}\left(t\right)\right|\mathrm{d}t}$$

(30)

where f_g represents the line frequency (50 Hz). $v_{\mathrm{CE}1}$ and $v_{\mathrm{CE}0}$ are the on-state voltage drops of the outer and neutral-point switches, respectively, and $v_{\mathrm{D}0}$ denotes the forward voltage drop of the neutral-point clamping diodes.

When the PFA-DPWM strategy is employed, the switches of a given phase leg remain inactive during one-third of the fundamental period. Throughout the remaining two-thirds of this period, the neutral-point switch and an outer switch each undergo one switching transition. Accordingly, the switching loss for a single-phase leg of the T-type inverter is formulated as

$$\begin{array}{ll}\hfill P_{\mathrm{sw}}& =2f_{\mathrm{g}}{\displaystyle \sum _{n=1}^{f_{\mathrm{s}}/(6f_{\mathrm{g}})}\left[E_{\mathrm{on}1}\left(n\right)+E_{\mathrm{off}1}\left(n\right)+E_{\mathrm{rr}1}\left(n\right)+E_{\mathrm{on}0}\left(n\right)+E_{\mathrm{off}0}\left(n\right)+E_{\mathrm{rr}0}\left(n\right)\right]}\\ & +2f_{\mathrm{g}}{\displaystyle \sum _{n=f_{\mathrm{s}}/(3f_{\mathrm{g}})}^{f_{\mathrm{s}}/(2f_{\mathrm{g}})}\left[E_{\mathrm{on}1}\left(n\right)+E_{\mathrm{off}1}\left(n\right)+E_{\mathrm{rr}1}\left(n\right)+E_{\mathrm{on}0}\left(n\right)+E_{\mathrm{off}0}\left(n\right)+E_{\mathrm{rr}0}\left(n\right)\right]}\end{array}$$

(31)

where f_s is the switching frequency. $E_{\mathrm{on}1}\left(n\right)$, $E_{\mathrm{off}1}\left(n\right)$, and $E_{\mathrm{rr}1}\left(n\right)$ are the turn-on, turn-off, and reverse-recovery losses of the outer switches during the n-th switching period, respectively. $E_{\mathrm{on}0}\left(n\right)$, $E_{\mathrm{o}\mathrm{ff}0}\left(n\right)$, and $E_{\mathrm{rr}0}\left(n\right)$ represent the analogous loss components for the neutral-point switches.

The filter inductor loss P_L, is primarily composed of copper and core losses, the values of which are typically obtained from the manufacturer’s specifications. Consequently, the total inverter loss is the summation of the conduction loss P_cond, switching loss P_sw, and filter inductor loss P_L, can be expressed as

$$P_{\mathrm{inv}}=3P_{\mathrm{cond}}+3P_{\mathrm{sw}}+3P_{\mathrm{L}}$$

(32)

Figure 10 illustrates the loss distribution for a T-type inverter operating with the FPA-DPWM strategy, as calculated by the aforementioned loss model. Compared to the conventional SVPWM strategy, the FPA-DPWM approach achieves a notable reduction in P_sw and P_rr. While this approach incurs a slight increase in diode conduction loss, the overall inverter loss is nevertheless markedly diminished.

5. Simulation and Experimental Results

To verify the PFA-DPWM strategy, a T-type three-level circuit topology is depicted in Figure 11. The system parameters for the experimental setup are summarized in

Table 5. Parameters of the system.

Parameters	Value
DC bus voltage	750 VDC
Three-phase output voltage	380 VAC
Rated power	120 kVA
Switching frequency	8 kHz
Output frequency	50 Hz
Three-phase filter inductor	40 μH
Three-phase filter capacitor	20 μF

.

5.1. Simulation Results

This paper uses MATLAB R2023b software for simulation. The simulated waveforms for the three-level inverter, operating under the proposed PFA-DPWM control strategy, are depicted in Figure 12. The analysis of these waveforms demonstrates that the PFA-DPWM algorithm dynamically identifies the phase interval corresponding to the peak absolute load current. Consequently, the power switches are clamped during this high-current interval, which substantially reduces the associated switching losses. Furthermore, the proposed three-level PFA-DPWM strategy demonstrates excellent voltage control performance.

5.2. Experimental Results

To verify the efficacy of the PFA-DPWM control strategy, an experimental platform for a 120 kVA T-type three-level inverter was established, as presented in Figure 13.

As shown in Figure 14, the integrated control unit is enclosed in a standard 3U chassis (Compliant with the 19-inch rack EIA-310 industrial standard).to suppress electromagnetic interference and enhance converter stability. Its core control board utilizes a Digital Signal Processor (DSP: TMS320F28335 Manufacturer: Texas Instruments, Dallas, TX, USA) and Field-Programmable Gate Array (FPGA: XC6SLX16-2FTG256I Manufacturer: Xilinx, San Jose, CA, USA) architecture.

Figure 15 and Figure 16 illustrate the steady-state experimental operational characteristics of the T-type inverter under half-load and full-load conditions, respectively. Under half-load (70 kW) and full-load (140 kW) operation, the measured THD of the line voltage u_ab is 2.07% and 1.82%, respectively, which demonstrates that the three-phase output voltage possesses excellent harmonic and steady-state characteristics.

Figure 17 illustrates the experimental waveforms of the T-type inverter under a transient load condition. When the load undergoes a step increase from 20 kW to 100 kW, the output line voltage u_ab exhibits a transient dip of approximately 65 V and recovers to its steady-state condition within 400 μs. This performance demonstrates the inverter’s fast dynamic response.

From Figure 18, the switching devices remain inactive for one-third of the fundamental period, centered around the interval where the phase current reaches its peak magnitude. In Figure 18b, the clamping interval of the phase-a PWM signal is shifted by φ = 30°, which aligns this interval with the peak of the phase current to achieve minimal switching losses. Simultaneously, the proposed PFA-DPWM strategy maintains favorable harmonic characteristics, and is demonstrated by the high-quality output waveforms.

6. Conclusions

This paper proposes a three-level power factor adaptive DPWM (PFA-DPWM) strategy developed for T-type inverters. A comprehensive analysis of the harmonic characteristics and switching losses is provided for various three-level DPWM strategies. The proposed PFA-DPWM consistently constructs the lower envelope of switching losses, achieving a reduction of up to 50% compared to conventional SVPWM. This is accomplished while maintaining low harmonic distortion, thereby striking a favorable balance between high efficiency and superior output quality.

Furthermore, a detailed analysis of different three-level carrier-based modulation schemes reveals that the line voltage THD for the PD scheme is significantly lower than that for the POD/APOD schemes, as its carrier harmonic common-mode components can be mutually canceled in the line voltages.

The simulation and experimental results confirm that the PFA-DPWM strategy successfully clamps the power switches during the one-third of the fundamental period aligned with the peak absolute load current, while also maintaining good harmonic performance for the three-level inverter output.