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Energies 2019, 12(23), 4585; https://doi.org/10.3390/en12234585

Article
Photovoltaic-Driven SiC MOSFET Circuit Breaker with Latching and Current Limiting Capability
Industrial Electronic Group, Miguel Hernandez University of Elche, 03202 Elche, Spain
*
Author to whom correspondence should be addressed.
Received: 30 October 2019 / Accepted: 29 November 2019 / Published: 2 December 2019

Abstract

:
This paper introduces a Solid State Circuit Breaker with Latching and Current Limiting capabilities for DC distribution systems. The proposed circuit uses very few electronic parts and it is fully analog. A SiC N-MOSFET driven by a photovoltaic driver and a maximum current detector circuit are the core elements of the system. This work details circuit operation under different conditions and includes experimental validation at 1 kVdc. Wide versatility, highly configurable, and very fast response, less than 1 µs in the case of short-circuit, are the most remarkable outcomes.
Keywords:
Solid State Circuit Breaker (SSCB); fault current limiter; DC power distribution; WBG semiconductors; SiC MOSFET

1. Introduction

The ever-increasing number of DC loads in the domestic, public, and industrial sectors, together with the need to use renewable energies efficiently, is leading to the emergence of DC microgrids and end user distribution systems at higher voltages [1,2,3,4,5,6]. One of the key aspects, and one of the most challenging issues in DC microgrids and distribution relates to the protection system design [7]. The differences with AC distribution systems, such as arcing at disconnection [8], large capacitive loads that require high inrush currents and also produce very fast and large discharge electrical currents during low impedance faults [9], limit the use of traditional AC protection methods [10]. Commercial protection devices for DC distribution are typically fuses, Molded Case Circuit Breakers (MCCBs) and Solid State Circuit Breakers (SSCBs), the last group being those that use power semiconductor devices to decrease the tripping time and to increase the current interruption capability [11,12]. Silicon Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices, with low switching times and low on-resistance, are only adequate in low voltage DC distribution systems [13], i.e., below few hundreds of volts, while appropriate high-voltage, high-current power semiconductors, e.g., thyristors, Insulated-Gate Bipolar Transistor (IGBT), Integrated Gate-Commutated Thyristor (IGCT), are required in larger systems [14]. However, Wide BandGap (WBG) FET power transistors, with enhanced maximum voltage blocking capabilities, short switching times, and low on-resistance, have found new opportunities for SSCB development at higher voltages where silicon counterparts were not suitable [15].
In [16], the authors describe and experimentally validate a Silicon Carbide (SiC) Junction Field-Effect Transistor (JFET) based circuit breaker. This circuit, that uses a normally-on device, lacks current limitation capabilities and it could require additional protection methods to limit input surge currents. The gate drive circuit uses a small isolated PWM DC/DC converter that it is activated when a large fault current is detected by sensing the voltage across the JFET. Another related activity has been reported in [17], it deals with a circuit breaker based on SiC Static Induction Transistors (SIT) that uses an advanced control method for the gate voltage to reduce the voltage overshot during turn-off. It requires a digital processor, a high-speed digital-to-analog converter, an auxiliary supply, and a current sensor. The concept has been evaluated with a 400 V and 12 A prototype for data center applications, proving to be effective reducing overvoltage and transient oscillation during the interruption process.
Gate drive circuits for SSCBs are also an important topic since their requirements are different to ones needed in other typical power electronic applications. In particular, in [18] the authors describe a gate driver circuit for series connected SiC MOSFETs used as solid state circuit breakers. In this context, a renewed interest in photonic power electronic devices has appeared [19]. In [20], the authors describe a bidirectional normally-on 1200 V SiC JFET circuit breaker that uses an optical signal to command the gate driver to turn off the power transistors; and more recently, in [21], an optically-isolated gate drive for SiC MOSFETs is investigated and compared with magnetically-coupled gate drivers.
Optically isolated photovoltaic drivers provide some advantages over other isolated driver circuits for SSCBs. Circuit breakers require isolation of DC signal, due to the long on or off periods. Unlike capacitive or transformer isolating circuits that require more complex signal refreshing circuits for DC signal isolation, photovoltaic circuits are well suited for this particular issue. They also have the capability to generate a variable analog signal which is required to operate the MOSFET in the linear region for current limiting applications. An additional benefit, that often is a drawback in other MOSFET driving applications, is the low photocell current that enables slow turn-on and enhances inrush current control and circuit stability. On the other hand, fast turn-off is desired to protect the system after load failure or off command. Thus, additional turn-off circuits are often employed, which in some cases are integrated on the photovoltaic driver. Authors introduced in [22] a new concept of DC protection which has been extended in this work.
To end this introductory section, the paper is organized as follows. Section 2 introduces the photovoltaic-driven Solid State Circuit Breaker with Latching and Current Limiting capabilities (SSCB-LCL). Section 3 details the different SSCB-LCL circuit configurations. Section 4 presents the setup and a main transistor robustness study. Section 5 illustrates the prototype design and explains the proposed test plan. Section 6 covers the experimental results and the subsequent discussion. The paper concludes with Section 6.

2. SSCB-LCL Description and Operating Principle

The proposed SSCB-LCL, represented in Figure 1, was developed using only discrete parts and in a simplified way operates as follows. If ILoad is lower than ILimit, the SSCB-LCL will work in nominal operation, as a closed switch with very low conduction losses. In case ILoad exceeds ILimit, the SSCB-LCL will limit the load current to ILimit during a preconfigured time. If the fault persists, after the preconfigured time has elapsed, the load will be disconnected from the input. External commands were also included for controlled load disconnection or restarting the SSCB-LCL.
M1 is an N-channel SiC MOSFET that is driven by PV1 and Q2 as the main current regulating element for ILED. R8 sets the maximum ILED and V1 and R2 provide isolated supply to PV1.
The current limiting loop comprises the dual matched NPN transistors, Q1-1 and Q1-2, RShunt, and biasing and gain resistors R3, R4, and R5. During an overcurrent, this arrangement creates a current feedback loop that forces M1 to operate in linear mode by changing VGS. This circuit contains very few components, does not require external supply, and provides large bandwidth control signal for Q2. In essence, Q1-1 controls ILED through Q2 to close the current limiting feedback loop when the voltage across R5 equals the voltage in RShunt. Under these circumstances, and assuming VEB(Q1-1) = VEB(Q1-2) and IB(Q1-1) = IB(Q1-2) = 0, the current is regulated to ILimit (Equation (1)). Assuming V(Z1) >> (ILoadRShunt + VEB(Q1-2)), IBias is given by Equation (2).
I L i m i t = I B i a s R 5 R S h u n t ,
I B i a s = V ( Z 1 ) R 3 .
tLatching is defined as the time elapsed from the instant when ILoad exceeds Ilimit until the moment when the latching circuit finally opens M1. The timing function is performed with R1 and C1 depending on the status of D1. Selecting R11 >> R1, V(Z1) >> V(D1) and assuming VBE(Q4) + V(R11) ≅ 1V, tLatching is approximated by Equation (3) and it can be easily adjusted by R1 and C1. The other parts, R11, R12, R13, R14, R15, R16, Q4, Q5, and D2, form an accurate latching circuit to maintain M1 in Off-state after tLatching has expired.
t L a t c h i n g = R 1 C 1 l n [ V ( Z 1 ) ] .
Z1 trims a proper voltage reference. The current source, J1-R10, was used to provide the bias current for Z1 and the rest of SSCB-LCL. This current must be carefully adjusted to avoid excessive losses in J1. For this reason, and due to the ILED current requirements, V1 is used for supplying ILED. The enable input of V1 provides the shutdown command (Off). In case of V1 failure, the SSCB-LCL will be automatically disconnected. An opto-isolated Reset (O1) input has been included for restarting the SSCB-LCL and a freewheeling diode (DFW) is used to handle inductive load currents.
Focusing on MOSFET driver, the schematic diagram of PV1 is shown in Figure 2a and the typical photocell current-to-voltage characteristics are shown in Figure 2b. Here, ILED is controlled linearly by IB(Q2) as given in Equation (4) (please refer to Figure 1 and Figure 2b). I L E D m a x takes place when Q2 is saturated (Equation (5)). Typically, ISC is highly linear with ILED (Equation (6)). The current-to-voltage dependence of a photocell can be represented by the single-diode cell model (Equation (7)) and the maximum voltage of PV1 is then given by (Equation (8)).
I L E D = β I B ( Q 2 ) ,
I L E D m a x = V 1 V E C ( Q 2 S a t ) V L E D R 8 ,
I S C = α I L E D ,
I P h C e l l = I S C I R ( e ( V P h C e l l · q k T ) 1 ) ,
V O C = k T q l n I S C I R .
Detailed MOSFET Turn-On and Turn-Off processes can be explained with the help of Figure 3a,b (Turn-On) and Figure 3c,d (Turn-Off). MOSFET Turn-On using a photocell can be simplified as the Ciss charging with a constant current, Isc. Two terms are clearly identified, t d O n and tturn-On. t d O n depends on Q G ( V t h ) (please refer to Figure 2c), and it is approximated by Equation (9). It could be adjusted with R8 by modifying I L E D m a x . On the other hand, tturn-On, could be approximated by Equation (10) and it can be also varied with R8. The linear operation of M1 can be achieved by keeping VGS between the Vth and VOC.
t d O n Q G ( V t h ) I S C ,
t t u r n O n Q G ( V O C ) Q G ( V t h ) I S C .
By contrast, MOSFET Turn-off can be seen as the Ciss discharging through the equivalent resistance R t u r n O f f ( O f f ) . The process can be idealized using two time intervals, t d O f f and tturn-Off. t d O f f is the time required to discharge CISS from VOC to Vgp. It strongly depends on RG and R T u r n O f f ( O f f ) (please refer to Figure 3c,d), and it could be estimated by Equation (11). In addition, Vgp can be expressed in terms of Vth, g f s , and I M 1 as in Equation (12).
t d O f f = ( R G + R t u r n O f f ( O f f ) ) C I S S l n V O C V g p ,
V g p = V t h + I M 1 g f s .
Further, assuming inductive clamping behavior, tturn-Off can be split into two additional terms, trv and tfi, which can be expressed as Equation (13) (please refer to Figure 3d).
t t u r n O f f = t r v + t f i = ( R G + R t u r n O f f ( O f f ) ) · ( C R S S V i n V g p + C I S S l n V g p V t h ) .
In response to an overcurrent fault, the SSCB-LCL operates in four different states, which are identified as On-state, Delay State, Current Limiting State, and Off-State. Please refer to Figure 4 for the equivalent schematic of each state.
During On-State, M1 is fully on and ILoad shall remain below ILimit. Under these conditions, Q1-1 is off, Q2, which is in saturation mode, provides ILEDmax and VGS = VOC. Further, D1 forces C1 to keep discharged and Q4 remains off. Please refer to Figure 4a.
Just after ILoad exceeds ILimit, the SSCB-LCL enters in Delay State, I f a u l t flows through M1 even though ILED has been removed. The interval in Delay State is defined by t d O f f . Further, D1 turns off and C1 starts charging. Please refer to Figure 4b.
After Delay State the SSCB-LCL automatically enters in Current Limiting State. In this state, IB(Q2) is adjusted to keep ILimit flowing through M1 by operating it in linear region (Equation (1)). Current Limiting State automatically expires after tLatching (Equation (3)). At this point, V(R1) turns on Q5 and D2, then the SCCB-LCL latches in Off-State (refer to Figure 4d). Current Limiting State can be used, among other things, to limit inrush current with capacitive loads.
An external Reset is required to discharge C1 to turn on the SSCB-LCL again. Please refer to Figure 1.

3. SSCB-LCL Circuit Configuration

The SSCB-LCL allows different configurations by selecting RG, R1, and C1. The three main configurations were named STO with Current Limitation; FTO with Current Limitation; FTO without Current Limitation (circuit breaker). The transient response is different for each configuration (please refer to Figure 5). These are described next:

3.1. STO with Current Limitation

This configuration is devised to provide smooth transition from Delay State to Current Limiting State (refer to Figure 5a). For this purpose, a large RG value is used, typically above few kΩ. The larger RG, the smoother the transition is to Current Limiting State and less overshot occurs; however, t d O f f S T O increases proportionally and its value must be carefully selected to avoid excessive delay. Under these conditions, R T u r n O f f ( O f f ) < < R G applies and t d O f f S T O is eventually approximated by Equation (14).
t d O f f S T O = R G · C I S S · l n V O C V g p .

3.2. FTO with Current Limitation

This circuit configuration, which main waveforms are represented in Figure 5b, is intended to minimise t d O f f F T O by eliminating RG. In this case, t d O f f F T O could be approximated by Equation (15). It is also worth indicating that M1 turns off completely before entering in Current Limiting State, so, t d O n (Equation (9)) and t T u r n O n (Equation (10)) apply after the current fault.
t d O f f F T O = R T u r n O f f ( O f f ) · C I S S · l n V O C V g p .
In both configurations, STO with current limitation and FTO with current limitation, t d l m t , and tlmt can be approximated in terms of M1 gate charge and ISC as indicated by Equations (16) and (17), respectively.
t d l m t = Q G ( V O C ) I S C ,
t l m t = R 1 C 1 l n [ V ( Z 1 ) ] Q G ( V O C ) I S C .

3.3. FTO without Current Limitation (Circuit Breaker)

The SSCB-LCL can also be configured as a circuit breaker selecting the tLatching shorter than t d O n . This feature, combined with Fast Turn-Off, is interesting to provide high-speed protection (please refer to Figure 5c for the main waveforms). This particular configuration must be adopted in applications where the appearance of a low inductance short-circuit is feasible.

4. Materials and Methods

4.1. Setup and Main Transistor Robustness

Regarding the experimental setup, a Keysight N8937A power supply unit was used. A bank of six 590 uF capacitors (947D591K132DJRSN—Cornell Dubilier) is connected in parallel with the power supply. The load consists in a bank of 10 Multicomp MC14683 power resistors. It performs 1 kW nominal power capability at 1 kV with 1.95 mH parasitic series inductance, and an isolated FPGA controlled driver allows configurable resistor shunting to produce different step load (SL) conditions. The oscilloscope used is a 1 GHz analog bandwidth mixed domain oscilloscope (Tektronix MDO3104) with high-voltage differential probes (THDP0200 and THDP0100) and current probes (TCP0030A and TCP303). Please refer to Figure 6 for a simplified setup schematic.
The Wolfspeed C2M0080120D was chosen for M1. Its robustness under high power dissipation conditions [23,24] makes it an excellent choice in the required power ratio.
Two critical conditions must be taken into account to guarantee M1 robustness, operation in linear mode and short-circuit repetition capability.
For the first condition and to prevent M1 damage by excessive energy dissipation, all time and current limits were set in compliance with the manufacturer’s SOA, which means that selected limitation currents in the following tests are well below the specified current for switching applications shown in datasheets.
For the second condition, a C2M0080120D short circuit study was carried out. The study covers C2M0080120D ageing after 200 short-circuits at a VDS = 1000 V with a VGS = 8.4 V and a short-circuit time of 1.5 µs, longer than real response time in FTO without Current Limitation mode. Tests were realized at the Center of Reliable Power Electronics at the Aalborg University. Figure 7 shows the waveform evolution from the first and last (200) short circuit performed in these tests.
The data concludes that C2M0080120D is capable of withstanding at least 200 short-circuits at VDS = 1000 V without appreciable degradation, resulting a longer useful life than the mechanical devices. In addition, the VGS = 8.4 V condition means a reduction in the peak short-circuit current and shorter transition times according to Equations (11), (14) and (15). This condition furthermore allows low on-losses in low power range. DFW partly alleviates the overvoltage when inductive loads are switched off. In [25] a new “soft turn-off” technique is proposed in order to reduce the voltage overshoot and short circuit peak current. In this work, the use of Digital Signal Processor to control the operation of the SSCB also allows other enhanced protection functions. A more detailed analysis of the robustness of C2M0080120D at 1000 V is presented in [26] where based on the aging parameters (VGS(TH), IDSS, and Ron) analysis concluded that the C2M0080120D is capable to support, at least, 200 short circuits at 1000 V with 1.5 µs duration.

4.2. SSCB-LCL Design and Test Plan

An experimental prototype of the proposed SSCB-LCL was designed and implemented (please refer to Figure 8). Main part references are the following: M1 is Wolfspeed C2M0080120D; Vishay VOM1271 as PV1; 1N758 as Z1; USCi UJN1205K as J1, Traco Power TMR1-1211 as V1 was used because it provides an on/off control input; Analog Devices MAT03 as Q1-1 and Q1-2; and Bourns PWR4412-2SCR0500F as RShunt.
Z1 was biased with 1 mA while the whole biasing current flowing through J1-R10 was 1.2 mA, so at 1 kV input voltage, J1 dissipates around 1.2 W. On the other hand, IBias was adjusted to 145 µA. The values of R5, R1, C1, and RG were chosen depending on the performed test. Table 1 gathers all the relevant information of those values in each particular test.
The power loss of the device at nominal current, 1 A, is dominated by three factors. First, MOSFET conduction losses that are less than 0.1 W. The C2M0080120D equivalent on resistance, in conditions of VGS = 8.5 V and a current of 1 A, is below 100 mΩ according to the manufacturer’s data. Second, the current sink J1-R10 dissipates around 1.2 W. Finally, the ancillary power supply specified 0.23 W of typical power losses. This eventually results in 1.5 W estimated power losses of the whole circuit.
Taking into account these considerations, the test plan was divided into three main groups: STO with Current Limitation under different soft-overload faults and parameter sweeps (from Test I to Test V); FTO with Current Limitation under soft-overload fault (Test VI); FTO without Current Limitation (circuit breaker) under short-circuit fault (Test VII) and telecommand test under soft-overload fault (Test VIII). All tests were carried out at 1 kV and the complete test description can be found in Table 1.

5. Experimental Results and Discussion

To guarantee the long-term reliability, ILimit and tLatching (from Test I to Test VI) were configured taking into account the Safe Operating Area (SOA) of M1 plus some security margin (please refer to Figure 9).

5.1. Basic Operation

The aim of this test was to corroborate the predicted circuit operation, especially the relation between ILED and the SSCB-LCL response. As can be observed in Figure 10a, ILED is I L E D m a x during On-State and it is quickly removed when the fault is detected and it remains zero during t d O f f . Then, it increases as the circuit enters into Current Limiting State, keeping M1 in linear operation. Finally, ILED goes to zero again when tlatching elapses.

5.2. RG Sweep

The objective was to observe the circuit response with different RG values but keeping the same Ilimit, tlatching, and step load. As can be observed in Figure 10b, t d O f f S T O increases with RG but t d l m t remains similar in all cases, as predicted by Equations (14) and (16). Since tlmt is the same in all cases, M1 experiences similar power stress during the current limiting state. Calculated and measured values for t d O f f S T O and t d l m t are collected in Table 2. The following manufacturer’s values were used for theoretical calculations: VOC = 8.4 V; ISC = 15 µA; CISS = 2 nF; Vth = 2.4 V; gfs = 8 A/V. QG(VOC) = 20 nC; QG(Vth) = 8.5 nC.

5.3. Overload Sweep

It was planned to observe the sensitivity of the SSCB-LCL to detect currents above Ilimit, which were set to 1.5A. As can be seen in Figure 10c, only a small variation of t d O f f S T O is expected due to the change in Vgp (Equation (12)) produced by the different I f a u l t . Obviously, M1 power dissipation increases as the load value in fault conditions decreases.

5.4. t L a t c h i n g Sweep

This test was performed to assess different tLatching in the STO with Current Limitation configuration. As reported in Table 2, calculated values (Equation (3)) are in good agreement with measured tLatching. Figure 11d shows ILoad and R1 voltage, which is a representative variable of the latching circuit.

5.5. I L i m i t Sweep

In this test, several ILimit (Equation (1)) were adjusted by modifying R5 while keeping IBias = 145 µA. As can be observed in Table 2, good agreement is found between calculated and measured ILimit, which also can be seen in Figure 11a.

5.6. FTO with Current Limitation

Test VI was carried out to evaluate the FTO with Current Limitation under soft-overload fault. For this test, RG was set to 0 Ω. Table 2 and Figure 11b show the main results. It is worth to note the effect of M1 source inductance, Ls, that creates a VDS overvoltage during the turn-off.

5.7. Short-Circuit

This test was proposed to evaluate the circuit response against a short-circuit event. In order to prevent linear operation of the MOSFET at such extreme conditions, FTO without Current Limitation configuration was chosen. As shown in Figure 11c, t d O f f F T O is less than 1 µs, because Vgp (Equation (12)) goes closely to VOC and gate discharge current tends to increase because of the source inductance effect.

5.8. Tele Command Test

Finally, Test VIII was performed to check the proper operation of Tele-commands. As represented in Figure 11d, a soft-overload (t = 1.7 s) produces the load disconnection. Then, fault condition extinguishes (t = 4.5 s) and the Reset command turns on (t = 8.6 s) the SSCB-LCL again. The Off signal (t = 12 s) finally switches off the SSCB-LCL.

6. Conclusions

This work deals with a Solid State Circuit Breaker with latching and current limiting capabilities. The most remarkable features of the circuit proposed are different configurations by changing simple component values, low power consumption, few discrete parts used, and easy parameter adjustment, i.e., current limit threshold and latching time. Theoretical assumptions and models were demonstrated with an experimental setup, and a large number of different tests were included, including the fast turn-off response under short-circuit events, less than 1 µs, and remote control at 1 kVdc. In order to explore the robustness of a particular device (i.e., C2M0080120D), the circuit test was performed close its maximum voltage limit, but voltage and current should be derated according to the final application. This circuit allows easy voltage and current scalability using an appropriate power MOSFET selection and gate driver design.

Author Contributions

D.M., A.G. and J.M.B. conceived the idea, designed the experiment, guided the experiment, and wrote the manuscript; D.M. and R.G. conducted most of the validation test. All authors read and approved the manuscript.

Funding

This research was partially funded by Spanish Ministry of Economy and Competitiveness through the research project ESP2015-68117-C2-2-R.

Acknowledgments

The authors would like to thank the help provided by the Center of Reliable Power Electronics (CORPE), especially to Francesco Iannuzzo, to conduct SiC MOSFET endurance tests under repetitive short-circuit conditions during D. Marroqui’s doctoral research stay at Aalborg University.

Conflicts of Interest

The authors declare no conflict of interest.

Abbreviations

CISSM1 input capacitance.
CRSSM1 reverse transfer capacitance.
gfsM1 transconductance.
ILoadLoad current.
ILimitProgrammed current limit.
I f a u l t Fault current.
IBiasBias current of current limiting circuit.
ILEDPV1 light emitting diode current.
I L E D m a x Maximum PV1 light emitting diode current.
ISCPV1 photocell short-circuit current.
IRPV1 photocell diode saturation current.
M1Main power transistor.
PV1Photovoltaic driver.
Q G ( V t h ) M1 gate charge at its threshold voltage.
Q G ( V o c ) M1 gate charge at the open circuit voltage of the PV1 photocell.
RShuntShunt resistor.
RGM1 gate resistor.
R T u r n O f f ( O f f ) Equivalent resistance of PV1 turn-off circuit during off state.
R T u r n O f f ( O n ) Equivalent resistance of PV1 turn-off circuit during on state.
tLatchingLatching time.
t d O n Turn-on delay.
t d O f f Turn-off delay.
t d O f f S T O Turn-off delay in STO configuration.
t d O f f F T O Turn-off delay in FTO configuration.
t d l m t Current limitation response time.
tlmtLimitation time.
tturn-OnTurn-on time.
tturn-OffTurn-off time.
trvVoltage rise time.
tfiCurrent fall time.
VGSM1 gate-source voltage.
VgpM1 gate-source plateau voltage.
V(Z1)Reference voltage.
VLEDPV1 light emitting diode forward voltage
V1Auxiliary power supply.
VOCPV1 photocell open circuit voltage.
VthM1 threshold voltage.
VinSSCB-LCL input voltage.
αPV1 light emitting diode current to photocell current.
βBipolar junction transistor current gain.
kBoltzmann’s constant.
qElectron charge.
FTOFast Turn Off.
STOSlow Turn Off.

References

  1. Hatziargyriou, N.D. Microgrids: An Overview of Ongoing Research, Development, and Demonstration Projects Environmental Energy Technologies Division. IEEE Power Energy Mag. 2007, 5, 78–94. [Google Scholar] [CrossRef]
  2. Kakigano, H.; Miura, Y.; Ise, T. Low-voltage bipolar-type dc microgrid for super high quality distribution. IEEE Trans. Power Electron. 2010, 25, 3066–3075. [Google Scholar] [CrossRef]
  3. Elvira, D.G.; Blaví, H.V.; Pastor, À.C.; Salamero, L.M. Efficiency optimization of a variable bus voltage DC microgrid. Energies 2018, 11, 3090. [Google Scholar] [CrossRef]
  4. Madduri, P.A.; Poon, J.; Rosa, J.; Podolsky, M.; Brewer, E.A.; Sanders, S.R. Scalable DC Microgrids for Rural Electrification in Emerging Regions. IEEE J. Emerg. Sel. Top. Power Electron. 2016, 4, 1195–1205. [Google Scholar] [CrossRef]
  5. Rodriguez-Diaz, E.; Chen, F.; Vasquez, J.C.; Guerrero, J.M.; Burgos, R.; Boroyevich, D. Voltage-Level Selection of Future Two-Level LVdc Distribution Grids: A Compromise between Grid Compatibiliy, Safety, and Efficiency. IEEE Electrif. Mag. 2016, 4, 20–28. [Google Scholar] [CrossRef]
  6. Ryu, M.-H.; Kim, H.-S.; Baek, J.-W.; Kim, H.-G.; Jung, J.-H. Effective Test Bed of 380-V DC Distribution System Using Isolated Power Converters. IEEE Trans. Ind. Electron. 2015, 62, 4525–4536. [Google Scholar] [CrossRef]
  7. Salomonsson, D.; Söder, L.; Sannino, A. Protection of low-voltage DC microgrids. IEEE Trans. Power Deliv. 2009, 24, 1045–1053. [Google Scholar] [CrossRef]
  8. Chae, S.; Park, J.; Oh, S. Series DC Arc Fault Detection Algorithm for DC Microgrids Using Relative Magnitude Comparison. IEEE J. Emerg. Sel. Top. Power Electron. 2016, 4, 1270–1278. [Google Scholar] [CrossRef]
  9. Zhang, L.; Tai, N.; Huang, W.; Liu, J.; Wang, Y. A review on protection of DC microgrids. J. Mod. Power Syst. Clean Energy 2018, 6, 1113–1127. [Google Scholar] [CrossRef]
  10. Bui, D.M.; Chen, S.-L.; Lien, K.-Y.; Jiang, J.-L. Fault protection solutions appropriately used for ungrounded low-voltage AC microgrids. In Proceedings of the 2015 IEEE Innovative Smart Grid Technologies-Asia (ISGT ASIA), Bangkok, Thailand, 3–6 November 2015; pp. 1–6. [Google Scholar]
  11. Shukla, A.; Demetriades, G.D. A Survey on Hybrid Circuit-Breaker Topologies. IEEE Trans. Power Deliv. 2015, 30, 627–641. [Google Scholar] [CrossRef]
  12. Javed, W.; Chen, D.; Farrag, M.E.; Xu, Y. System configuration, fault detection, location, isolation and restoration: A review on LVDC microgrid protections. Energies 2019, 12, 1001. [Google Scholar] [CrossRef]
  13. Izquierdo, D.; Barrado, A.; Raga, C.; Sanz, M.; Lázaro, A. Protection devices for aircraft electrical power distribution systems: State of the art. IEEE Trans. Aerosp. Electron. Syst. 2011, 47, 1538–1550. [Google Scholar] [CrossRef]
  14. Chen, Z.; Yu, Z.; Zhang, X.; Wei, T.; Lyu, G.; Qu, L.; Huang, Y.; Zeng, R. Analysis and Experiments for IGBT, IEGT, and IGCT in Hybrid DC Circuit Breaker. IEEE Trans. Ind. Electron. 2018, 65, 2883–2892. [Google Scholar] [CrossRef]
  15. Shen, Z.J.; Sabui, G.; Miao, Z.; Shuai, Z. Wide-bandgap solid-state circuit breakers for DC power systems: Device and circuit considerations. IEEE Trans. Electron Devices 2015, 62, 294–300. [Google Scholar] [CrossRef]
  16. Miao, Z.; Sabui, G.; Roshandeh, A.M.; Shen, Z.J. Design and Analysis of DC Solid-State Circuit Breakers Using SiC JFETs. IEEE J. Emerg. Sel. Top. Power Electron. 2016, 4, 863–873. [Google Scholar] [CrossRef]
  17. Sato, Y.; Tanaka, Y.; Fukui, A.; Yamasaki, M.; Ohashi, H. SiC-SIT circuit breakers with controllable interruption voltage for 400-V DC distribution systems. IEEE Trans. Power Electron. 2014, 29, 2597–2605. [Google Scholar] [CrossRef]
  18. Ren, Y.; Yang, X.; Zhang, F.; Wang, K.; Chen, W.; Wang, L.; Pei, Y. A Compact Gate Control and Voltage-Balancing Circuit for Series-Connected SiC MOSFETs and Its Application in a DC Breaker. IEEE Trans. Ind. Electron. 2017, 64, 8299–8309. [Google Scholar] [CrossRef]
  19. Mazumder, S.K. An Overview of Photonic Power Electronic Devices. IEEE Trans. Power Electron. 2016, 31, 6562–6574. [Google Scholar] [CrossRef]
  20. Veliadis, V.; Steiner, B.; Lawson, K.; Bayne, S.B.; Urciuoli, D.; Ha, H.C. Suitability of N-ON Recessed Implanted Gate Vertical-Channel SiC JFETs for Optically Triggered 1200 v Solid-State Circuit Breakers. IEEE J. Emerg. Sel. Top. Power Electron. 2016, 4, 874–879. [Google Scholar] [CrossRef]
  21. Wilkins, M.M.; Ishigaki, M.; Provost, P.O.; Masson, D.; Fafard, S.; Valdivia, C.E.; Dede, E.M.; Hinzer, K. Ripple-free boost-mode power supply using photonic power conversion. IEEE Trans. Power Electron. 2019, 34, 1054–1064. [Google Scholar] [CrossRef]
  22. Marroquí, D.; Garrigós, A.; Blanes, J.M.; Gutiérrez, R.; Maset, E.; Ramírez, D. SIC based solid state protections switches for space applications. In Proceedings of the 2017 19th European Conference Power Electronics Applications EPE 2017 ECCE Europe, Warsaw, Poland, 11–14 September 2017; pp. 1–8. [Google Scholar]
  23. Li, H.; Yu, R.; Zhong, Y.; Yao, R.; Liao, X.; Chen, X. Design of 400 V Miniature DC Solid State Circuit Breaker with SiC MOSFET. Micromachines 2019, 10, 314. [Google Scholar] [CrossRef] [PubMed]
  24. Wang, J.; Jiang, X.; Li, Z.; Shen, Z.J. Short-Circuit Ruggedness and Failure Mechanisms of Si/SiC Hybrid Switch. IEEE Trans. Power Electron. 2019, 34, 2771–2780. [Google Scholar] [CrossRef]
  25. Qin, H.; Mo, Y.; Xun, Q.; Zhang, Y.; Dong, Y. A Digital-Controlled SiC-Based Solid State Circuit Breaker with Soft Switch-Off Method for DC Power System. Electronics 2019, 8, 837. [Google Scholar] [CrossRef]
  26. Marroqui, D.; Garrigos, A.; Blanes, J.M.; Gutierrez, R.; Maset, E.; Iannuzzo, F. SiC MOSFET vs SiC/Si Cascode short circuit robustness benchmark. Microelectron. Reliab. 2019, 100, 113429. [Google Scholar] [CrossRef]
Figure 1. Electrical schematic of the proposed Solid State Circuit Breaker with Latching and Current Limiting capabilities (SSCB-LCL).
Figure 1. Electrical schematic of the proposed Solid State Circuit Breaker with Latching and Current Limiting capabilities (SSCB-LCL).
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Figure 2. (a) Photovoltaic driving circuit block diagram. (b) Ideal current-to-voltage PV1 characteristic. (c) Gate charge characteristic.
Figure 2. (a) Photovoltaic driving circuit block diagram. (b) Ideal current-to-voltage PV1 characteristic. (c) Gate charge characteristic.
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Figure 3. (a) Simplified Turn-On circuit; (b) Turn-On transient sketch; (c) simplified Turn-Off circuit; (d) Turn-Off transient sketch.
Figure 3. (a) Simplified Turn-On circuit; (b) Turn-On transient sketch; (c) simplified Turn-Off circuit; (d) Turn-Off transient sketch.
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Figure 4. Equivalent circuits of each SSCB-LCL state; (a) On-State; (b) Delay state; (c) Current Limiting State; (d) Off-State.
Figure 4. Equivalent circuits of each SSCB-LCL state; (a) On-State; (b) Delay state; (c) Current Limiting State; (d) Off-State.
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Figure 5. Idealized waveforms of each circuit configuration. (a) STO with Current Limitation; (b) FTO with Current Limitation; (c) FTO without Current Limitation (circuit breaker).
Figure 5. Idealized waveforms of each circuit configuration. (a) STO with Current Limitation; (b) FTO with Current Limitation; (c) FTO without Current Limitation (circuit breaker).
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Figure 6. Sketch of the setup for the SSCB-LCL (DUT) validation.
Figure 6. Sketch of the setup for the SSCB-LCL (DUT) validation.
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Figure 7. Short-circuit C2M0080120D test waveforms. (a) In dark blue dashed line VDS in short circuit 1 (200 V/div); in cyan blue solid line VDS in short circuit 200 (200 V/div); in dark green dashed line IS in the short circuit 1 (10 A/div); in light green solid line IS in the short circuit 200 (10 A/div). Time Scale: 0.5 µs/div. (b) In light grey dashed line VGS in the short circuit 1 (10 A/div); In dark grey solid line VGS in the short circuit 200 (2 V/div). Time scale: 0.5 µs/div.
Figure 7. Short-circuit C2M0080120D test waveforms. (a) In dark blue dashed line VDS in short circuit 1 (200 V/div); in cyan blue solid line VDS in short circuit 200 (200 V/div); in dark green dashed line IS in the short circuit 1 (10 A/div); in light green solid line IS in the short circuit 200 (10 A/div). Time Scale: 0.5 µs/div. (b) In light grey dashed line VGS in the short circuit 1 (10 A/div); In dark grey solid line VGS in the short circuit 200 (2 V/div). Time scale: 0.5 µs/div.
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Figure 8. Implemented SSCB-LCL prototype.
Figure 8. Implemented SSCB-LCL prototype.
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Figure 9. C2M0080120D datasheet Safe Operation Area and theoretical performed test location.
Figure 9. C2M0080120D datasheet Safe Operation Area and theoretical performed test location.
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Figure 10. (a) Test I—Basic Operation. Top figure: ILED (4 mA/div). Middle figure: ILoad (0.5 A/div). Lower figure VDS(M1) (200 V/div). Time scale: 1 ms/div. (b) Test II—RG sweep. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 ms/div. (c) Test III—Overload sweep. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 ms/div. (d) Test IV—tLatching sweep Top figure: V(R1) (1 V/div). Lower figure: ILoad (500 mA/div). Time scale: 1 ms/div.
Figure 10. (a) Test I—Basic Operation. Top figure: ILED (4 mA/div). Middle figure: ILoad (0.5 A/div). Lower figure VDS(M1) (200 V/div). Time scale: 1 ms/div. (b) Test II—RG sweep. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 ms/div. (c) Test III—Overload sweep. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 ms/div. (d) Test IV—tLatching sweep Top figure: V(R1) (1 V/div). Lower figure: ILoad (500 mA/div). Time scale: 1 ms/div.
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Figure 11. (a) Test V—ILimit sweep. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time Scale: 1 ms/div. (b) Test VI—FTO with current limitation. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/division). Time scale: 1 ms/div. (c) Test VII—Short circuit. Top figure: ILoad (10 A/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 µs/div. (d) Test VIII—Tele Command Test. Top figure: Digital External Commands. Middle figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 s/div.
Figure 11. (a) Test V—ILimit sweep. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time Scale: 1 ms/div. (b) Test VI—FTO with current limitation. Top figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/division). Time scale: 1 ms/div. (c) Test VII—Short circuit. Top figure: ILoad (10 A/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 µs/div. (d) Test VIII—Tele Command Test. Top figure: Digital External Commands. Middle figure: ILoad (500 mA/div). Lower figure: VDS(M1) (200 V/div). Time scale: 1 s/div.
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Table 1. Test description.
Table 1. Test description.
DescriptionConstant ParametersVariable Parameter
STO with Current LimiterTest I
Basic Operation
SL = 1 to 1.66 A
t L a t c h i n g   =   4.5   ms
I L i m i t = 1.5 A
Load = 1000 to 600 Ω
R1 = 180 kΩ, C1 =10 nF
R5 = 527 Ω, RShunt = 50 mΩ
RG = 180 kΩ
Test   II
R G Sweep
SL   =   1   to   2   A
t L a t c h i n g   =   4.5   ms
I L i m i t = 1.5 A
Load = 1000 to 500 Ω
R1 = 180 k, C1 = 10 nF
R5 = 527 Ω, RShunt = 50 mΩ
R G = [50, 100, 180] kΩ
Test III
Overload Sweep
t L a t c h i n g   =   4.5   ms
I L i m i t = 1.5 A
R1 = 180 kΩ, C1 = 10 nF
R5 = 527Ω, RShunt = 50 mΩ
RG = 180 kΩ
LS = 1 A to [1.6, 2, 2.5, 3.3] A
Load = 1000 Ω to [600, 500, 400, 300] Ω
Test   IV
t L a t c h i n g Sweep
SL   =   1   to   2   A
I L i m i t = 1.5 A
Load = 1000 to 500 Ω
R5 = 527 Ω, RShunt = 50 mΩ
R1 = 180 kΩ, RG = 180 kΩ
t L a t c h i n g = [1.9, 4.1, 9.1] ms
C1 = [4.7, 10, 22] nF
Test   V
I L i m i t Sweep
SL   =   1   to   2   A
t L a t c h i n g = 4.5 ms
Load = 1000 to 500 Ω
R1 = 180 k, C1 = 10 nF
RG = 180 kΩ, RShunt = 50 mΩ
I L i m i t = [1.25, 1.53, 1.80] A
R5 = [430, 527, 620] Ω
Test VI
FTO with Current Limitation
SL   =   1   to   2   A
t L a t c h i n g   =   4.5   ms
I L i m i t = 1.5 A
Load = 1000 to 500 Ω
R1 = 180 k, C1 = 10 nF
R5 = 527 Ω, RShunt = 50 mΩ
RG = 0 Ω
Circuit BreakerTest VII
Short-circuit
SL   =   1   A   to   SC
I L i m i t = 1.5 A
Load = 1000 Ω to SC
R5 = 527 Ω, RShunt = 50 mΩ
R1 = 510 Ω, C1 = 1 nF
RG = 0 Ω
Test VIII
Tele Command
SL   =   1   to   2   A
I L i m i t = 1.5 A
Load = 1000 to 500 Ω
R5 = 527 Ω, RShunt = 50 mΩ
R1 = 510 Ω, C1 = 1 nF
RG = 0 Ω
Table 2. Theoretical and test measured results.
Table 2. Theoretical and test measured results.
DescriptionParameterVariableTheoreticalMeasured
STO with Current LimiterTest II
R G Sweep
t d O f f S T O RG50 kΩ127 µs146 µs
100 kΩ242 µs264 µs
180 kΩ427 µs462 µs
t d l m t ALL1.3 ms900 µs
Test IV
t L a t c h i n g Sweep
t L a t c h i n g C14.7 nF1.9 ms2.2 ms
10 nF4.1 ms4.0 ms
22 nF9.1 ms10.2 ms
Test V
I L i m i t Sweep
I L i m i t R5430 Ω1.25 A1.19 A
527 Ω1.53 A1.54 A
620 Ω1.80 A1.83 A
Test VI
Fast Turn-Off with Current Limitation
t d O f f S T O N/AN/A16 µs
t d O n N/A570 µs700 µs
t T u r n O n N/A770 µs700 µs
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