#### 3.1. Model Description

For optimizing performances of the 1T pixel, we have built a model allowing determination of linear conversion characteristics such as conversion gain (CG). The modeling approach is described as follows.

The first step is to consider the capacitances of the pixel structure and to establish an ac equivalent circuit for estimating the total capacitance of the transistor's floating body. It is this capacitance that plays the role of charge storage and determines the relationship between stored holes and the potential of the floating body.

Figure 4a shows the pixel structure with inherent capacitances. The pixel transistor has, beside its drain, gate, source and bulk having external connections, two internal nodes: its channel C and its floating body B' where holes can be stored in integration and readout modes.

Figure 4b presents the corresponding ac equivalent circuit for both integration and readout operations. It does not include drain-ground and gate-ground capacitances because they are short-circuited by bias voltages. The switching positions of

S_{WChS},

S_{WChD} and

SW_{S} of the equivalent circuit depend on the operating modes. In integration mode, as the transistor is off, both

SW_{ChS} and

SW_{ChD} are thus open. In readout mode,

SW_{ChS} and

SW_{ChD} are closed because the transistor is on (in saturation). It may look oversimplifying to assume the same potential for the source, the channel and the drain, but the situation is that the channel resistance of the on-state transistor is negligible (∼ 10

^{6} Ω) compared to the impedances of the in-pixel capacitances (∼ 10

^{10} Ω) at operating frequencies, and that

C_{OXeff} is effectively “short-circuited” by at least half of the channel resistance in parallel with it. Another way to see it is that the channel resistance imposes the C node to much lower impedance, like a “shield” to prevent effect of

C_{OXeff}. For

SW_{S}, it is open only in readout mode.

From the equivalent circuit of

Figure 4b, the total capacitance of the floating body

B', denoted

C_{B'}, can be written as:

It should be noted that in reset mode, when the stored charges are (normally) completely evacuated, C_{B}_{'}can be considered to be short-circuited. What is more important is readout-mode C_{B}_{'}, because it is related to the readout-determined conversion gain (CG) of the pixel, which will be expressed in (7).

The next step is to determine the pixel's linear conversion characteristics. The following describes how the conversion gain is determined. It is defined as:

where

V_{pix} is the pixel output voltage, N

_{ch} the number of the collected photo-generated charges being stored in the pixel's integration capacitance, and

Q_{ph} the quantity of the stored charges. For this 1T pixel, the integration capacitance is no other than

C_{B}_{'}. Thus the conversion gain can be expressed as:

On the other hand, a variation of floating body potential (due to stored charges) will induce a shift of the transistor's threshold voltage

V_{tn}, which can be seen from the following relationship [

7]:

where

Φ_{MS} is the work-function difference,

2Φ_{F} is the surface inversion potential (which is 2 times the difference between the Fermi level of the substrate and intrinsic silicon),

N_{B} the doping concentration of the transistor's (floating) body,

V_{B}_{'}the floating-body potential,

V_{S} the transistor's source potential,

C_{OXeff} the effective gate-oxide capacitance,

A_{G} the effective gate area,

Q_{ox} the oxide charge density and

Q_{shal} the shallow-implant charge density.

The derivative of

V_{tn} with respect to

V_{B}_{'} gives:

with:

and:

where

X_{dep} is the depletion-layer thickness between the transistor's channel and its floating body. It can be seen from (5) that increasing the floating body potential causes a lowering of the threshold voltage.

As the transistor in readout mode is biased with a constant gate voltage, and the drain current is function of (

V_{G} –

V_{S} –

V_{tn}), a decrease of

V_{tn} amounts to an equivalent increase in

V_{G}, i.e. – Δ

V_{tn} = Δ

V_{G}. Then, according to the source follower operation, we have:

where

A_{v} (∼ 0.9) is the source follower's voltage gain.

From (3), (5) and (6), we can rewrite the conversion gain as:

Finally this model may integrate models of involved parameters. For example,

C_{dep} in the above expression is related to the silicon surface potential, which in turn depends on properties of gate oxide and Si/SiO

_{2} interface. We have modeled

C_{dep} based on analytical descriptions in [

8,

9]. This has enabled us to analyze effects of process parameters.

It should be mentioned that capacitances in the silicon are voltage-dependent, especially when they result from lightly-doped regions, such as

C_{SB}_{'},

C_{B'D} and

C_{B'B}. It implies that the total capacitance

C_{B}_{'}may vary with the floating body potential. Consequently, the conversion linearity may degrade. However, as will be seen in the following subsection,

C_{SB'}, C_{B'D} and

C_{B'B} are much smaller than

C_{dep}. This means that

C_{B}_{'} ≈

C_{dep}. We obtain thus a simplified expression of CG:

The above expression does not include capacitances in the silicon. Therefore, there are no significant effects of stored charges and induced potential variations on CG. The estimated linearity error of conversion is about 2%.

The expression (8) allows rough estimation of CG. It predicts (especially for process optimization) that CG may be improved by increasing the gate-oxide thickness t_{ox}.