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Article

Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution

1
Algoritmi Centre, University of Minho, 4800-058 Guimarães, Portugal
2
Associação Laboratório Colaborativo em Transformação Digital—DTx Colab, 4800-058 Guimarães, Portugal
*
Author to whom correspondence should be addressed.
These authors contributed equally to this work.
Academic Editor: Angel Diéguez
Sensors 2022, 22(8), 2943; https://doi.org/10.3390/s22082943
Received: 10 March 2022 / Revised: 8 April 2022 / Accepted: 8 April 2022 / Published: 12 April 2022
Due to a point cloud’s sparse nature, a sparse convolution block design is necessary to deal with its particularities. Mechanisms adopted in computer vision have recently explored the advantages of data processing in more energy-efficient hardware, such as the FPGA, as a response to the need to run these algorithms on resource-constrained edge devices. However, implementing it in hardware has not been properly explored, resulting in a small number of studies aimed at analyzing the potential of sparse convolutions and their efficiency on resource-constrained hardware platforms. This article presents the design of a customizable hardware block for the voting convolution. We carried out an in-depth analysis to determine under which conditions the use of the voting scheme is justified instead of dense convolutions. The proposed hardware design achieves an energy consumption about 8.7 times lower than similar works in the literature by ignoring unnecessary arithmetic operations with null weights and leveraging data dependency. Access to data memory was also reduced to the minimum necessary, leading to improvements of around 55% in processing time. To evaluate both the performance and applicability of the proposed solution, the voting convolution was integrated into the well-known PointPillars model, where it achieves improvements between 23.05% and 80.44% without a significant effect on detection performance. View Full-Text
Keywords: deep learning; field-programmable gate array (FPGA); sparsity; voting convolution; 3D object detection models deep learning; field-programmable gate array (FPGA); sparsity; voting convolution; 3D object detection models
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MDPI and ACS Style

Pereira, P.; Silva, J.; Silva, A.; Fernandes, D.; Machado, R. Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution. Sensors 2022, 22, 2943. https://doi.org/10.3390/s22082943

AMA Style

Pereira P, Silva J, Silva A, Fernandes D, Machado R. Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution. Sensors. 2022; 22(8):2943. https://doi.org/10.3390/s22082943

Chicago/Turabian Style

Pereira, Pedro, João Silva, António Silva, Duarte Fernandes, and Rui Machado. 2022. "Efficient Hardware Design and Implementation of the Voting Scheme-Based Convolution" Sensors 22, no. 8: 2943. https://doi.org/10.3390/s22082943

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