1.1. Evolution of the CCD-ISIS
- Parallel/Partial Readout Imaging Scheme (PPR):This is the most common technique to increase the frame rate simply by reading out image signals in parallel through many readout taps, and/or partially only from a selected area in the imaging area.
- In situ Storage Imaging Scheme (ISIS):A number of storage elements are placed within or nearby each pixel to store a number of consecutively captured images. The ISIS camera operates at an ultra-high frame rate with a frame interval equal to the time required for signal electrons generated in photo-diodes move to the nearby storage elements [1–6].
- A BSI-ISIS with the maximum frame rate achievable by a current standard CCD technology.
- A BSI-ISIS with the theoretical maximum frame rate.
1.2. The Design Experience of ISIS-100M
2. General Description of the ISIS-100M
2.1. Plane and Cross Section Structure
2.2. Basic Performance
3. Technologies to Achieve Ultra-high Frame Rate
- Two-phase-transfer CCD: Although the two-phase transfer is a common CCD technology, it increases the frame rate when combined with differential driving voltage transfer. However, employment of the two-phase transfer functions to increase the frame rate by the combination with the complementary internal bus lines explained later. The contact structures between the polysilicon and metal layers are simplified, which makes it easy to employ multi-metal layers to reduce parasitic impedance in transfer of the driving voltages.
- Three-layer p-well design: An innovative design with three p-well layers is introduced to generate a smoothly changing potential gradient toward the collection gate and to protect the storage CCD channels from migration of generated photoelectrons. The p-well of each pixel has two holes: a large one at the collection gate is to introduce photoelectrons to the storage CCD channels on the front side; a small one at the drain to collect five percent of the generated photo-electrons to monitor in real time a sudden change in the average brightness, which serves as an index for occurrence of a target event.
- Curved CCD design: Since the very early development stage of the CCD-ISIS group, a curved design has been introduced to transfer photoelectrons smoothly and swiftly .
- Microlens array: In design of common imagers, microlens arrays are mainly used to increase the nominal fill factor. For BSI-ISIS, they contribute to pixel separation for oblique incident light to increase the frame rate.
- Wiring layout to minimize RC delay in driving voltage transfer: Attenuation of driving voltages of the ISIS-V12 is rather high, which limited the maximum frame rate for the full well capacity at 250,000 fps. We developed a simple yet accurate evaluation method to estimate the attenuation of the sensor without time-consuming full-scale circuit simulation .
- Complementary global bus-lines: An innovative, CCD-specific design is introduced to reduce the inductance of the two-phase bus lines. This is required to allow the high frequency current flows needed to drive the ISIS-100M at 100 Mfps.
4. Acceleration of Photo-Electrons Transport from the Backside to Collection Gate
4.1. Special P-well Layer Design
- To confine photo-electrons generated in the generation layer at the backside within the pixel area.
- To make a p-well protect the storage area from migration of signal electrons.
- To accelerate their horizontal transfer speed.
- To smoothly introduce them to the collection gate and to the input gate under the p-well.
- The first layer covers most of the pixel area except the collection gate, which creates a horizontal barrier.
- The second layer also covers most of the pixel area and also serves as a horizontal barrier. Besides, there are two trunk-like large holes stretching toward the top left and top right corner of the pixel, respectively. The holes were designed to have a widening exponential shape toward the collection gate to generate a potential gradient vertically downward the collection gate. The bifurcation of this layer design is introduced to separate the electron path to the collection gate from the path to the drain through the small hole for a video trigger.
- The last p-well layer consists of a finger-like structure around the pixel perimeter to define pixel boundaries. It also has one trapezoid stretching downward from the small hole to separate the electron paths.
4.2. Electron Transit Time and Efficiency of Micro-Lens Array
- Ten thousands photoelectrons are generated at once at and distributed uniformly over the back surface of each pixel.
- A microlens on the pixel collects and uniformly distributes the electrons in the central area of the back surface: the area is 50% or 20% of the back surface as depicted in Figure 7.
- Without the microlens, 90% of electrons are transferred within 5 ns.
- The microlens with a light collection rate of 50% is not so effective. However, if the collection rate is 20%, the efficiency is significantly improved and 97.2% of electrons reach the collection gate within 5 ns.
- It is impossible to achieve transfer of 100% of electrons for 100 Mfps.
- More than 90% can be transferred.
- If we employ a microlens array and an appropriate post-processing technology, the frame rate very close to 100 Mfps can be achieved.
5. Technology to Deliver Driving Voltages
5.1. Metal Layout to Reduce RC Delay in Driving Voltage Transfer
- An additional aluminum layer used as bus lines placed on the imaging area.
- Direct bonding of wires from external circuitry to each bus line.
5.2. Application of Differential Bus Lines
- In order to reduce RC delay, the global bus lines have to be wide and thick enough to reduce their resistances. This makes reactance part comparable or even greater than resistance part in the parasitic impedance.
- As the frequency increases, driving voltage waveform contains higher frequency components, which makes the inductance effect more significant.
- Skin effect appears on resistance for frequencies larger than 20 MHz. However, up to 100 MHz, the effect can be neglected in practical designs.
- Effect of magnetic inductance is very large. The condition ωL = 0.1R is obtained at a frame rate of 2 Mfps, much slower than our design target of 100 Mfps.
5.3. Crossed Bundling
6. CCD-CMOS Hybrid Ultra-High-Speed Image Sensor: RA-ISIS
- With a gap narrower than 0.2 μm between adjacent transfer gate electrodes, a smoothly changing potential profile is created in the buried CCD channel. Recent deep-submicron CMOS processes allow fabrication of polysilicon gates with the gap less than 0.2 μm.
- Only minor process modification is required. To increase full well capacity and create a smooth channel potential beneath the poly-poly gap, thickening of the oxide insulation layer is necessary.
- Various other CCD related technologies had been introduced to the advanced CMOS image sensor process such as deep implanting, floating diffusion amplifier, correlated double sampling technique, etc.
- Advanced CMOS processes utilize four or more metal layers, from which two upper metal layers are allocated to the crossed differential internal bus lines to significantly reduce the inductance.
- The very fine design rule makes possible scaling of the CCD-ISIS, which is the simplest way to increase the maximum frame rate. For example, when the driving voltage transfer is the limiting factor on the maximum frame rate, by reducing the width of the chip to a half of the original size, resistance and inductance of the internal bus lines and the capacitance of the buried CCD channels all reduces to the halves of the original values. As a result, the total power load for the driving voltage transfer is reduced to a quarter, which increases the maximum frame rate four times.
- Incorporating CMOS readout technology with CCD in situ storage, we can obtain an ultimate high speed image sensor with flexible and high speed readout by CMOS technology and ultra-high-speed and superior image quality by CCD technology.
7. Other Technical Problems
- Heat generation
- Removal of positive charge carriers (holes) from the backside
- Compact high-power driver IC
- Integrated packaging
- The time required for photo-electrons generated at the backside to reach the storage CCD on the front side is minimized by employment of the wafers with double-epi layers, the special three-layer p-well design, the curved CCD design and a microlens array.
- The RC-delay is minimized by introducing one additional layer for the internal bus lines and directly bonding them to wires from external circuitry. A simple estimation method developed by the authors contributes to optimization of the metal wiring.
- Inductance of the internal bus lines is minimized by the proposed crossed differential bus lines, which is specifically efficient to drive CCDs.
- The chip size is minimized to fabricate the CCD-ISIS using an advanced sub-micron CMOS image sensor process.
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|Sensor/Camera||Frontside illuminated||Backside illuminated|
|ISIS-V2 [2,3]||ISIS-V4 +||ISIS-V12 [5,13]||ISIS-100M*|
|Pixel count (pixels)||81,120 (312 × 260)||302,400 (420 × 720)||201,600 (480 × 420)||140,800 (440 × 320)|
|Maximum frame rate||1 Mfps||1 Mfps||1 Mfps||100 Mfps|
|Technologies for high sensitivity||N/A||N/A||CCM/Backside illumination/Cooling||Backside illumination/Cooling|
|Frame Rate||30–100,000,000 fps|
|Pixel Count||440 × 320 (=140,800) pixels|
|Pixel Size||50.4 × 50.4 μm2|
|CCD element size||3.6 × 3.6 μm2|
|Number of Stored Images||126 frames|
|Full well Capacity||8,000 electrons|
|Grey Level||>9 bits|
|On-chip trigger system||Installed|
|Transfer Scheme||2-phase transfer for VCCD, voltage swing 10 V|
4-phase transfer for HCCD, voltage swing 5 V
|Magnetic energy (ME) profile|
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