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Keywords = semi-superjunction

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15 pages, 6026 KB  
Article
A 3.3 kV SiC Semi-Superjunction MOSFET with Trench Sidewall Implantations
by Marco Boccarossa, Kyrylo Melnyk, Arne Benjamin Renz, Peter Michael Gammon, Viren Kotagama, Vishal Ajit Shah, Luca Maresca, Andrea Irace and Marina Antoniou
Micromachines 2025, 16(2), 188; https://doi.org/10.3390/mi16020188 - 6 Feb 2025
Cited by 3 | Viewed by 3326
Abstract
Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents [...] Read more.
Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (RDS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in RDS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in RDS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs. Full article
(This article belongs to the Special Issue SiC Based Miniaturized Devices, 3rd Edition)
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12 pages, 3372 KB  
Article
Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET
by Zhen Cao, Qi Sun, Chuanfeng Ma, Biao Hou and Licheng Jiao
Micromachines 2024, 15(3), 411; https://doi.org/10.3390/mi15030411 - 19 Mar 2024
Cited by 1 | Viewed by 1911
Abstract
This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing [...] Read more.
This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (RON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV2/RON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-RON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results. Full article
(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)
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