Search Results (3)

In recent years, the intelligent reflecting surface (IRS) has attracted increasing attention for its capability to intelligently reconfigure the wireless propagation channel. However, most existing works ignore the dynamic power consumption of IRS related to the phase shift configuration. This relationship gets even more intractable for a multi-bit IRS because of its nonlinearity and implicit form. In this paper, we investigate the beamforming optimization for multi-bit IRS-aided systems with the practical phase shift-dependent power consumption (PS-DPC) model, aiming at minimizing the power consumption of the system. To solve the implicit and nonlinear relationship, we introduce a selection matrix to explicitly represent the power consumption and the phase shift matrix of the IRS, respectively. Then, we propose a generalized Benders decomposition-based beamforming optimization algorithm in the single-user scenario. Furthermore, in the multi-user scenario, we design a coordinate descent-based algorithm and a genetic algorithm for the beamforming optimization. The simulation results show that the proposed algorithms significantly decrease the power consumption of the multi-bit IRS-aided systems. Full article

Future satellite platforms and 5G millimeter wave systems require Electronically Steerable Antennas (ESAs), which can be enabled by Microwave Liquid Crystal (MLC) technology. This paper reviews some fundamentals and the progress of microwave LCs concerning its performance metric, and it also reviews the MLC technology to deploy phase shifters in different topologies, starting from well-known toward innovative concepts with the newest results. Two of these phase shifter topologies are dedicated for implementation in array antennas: (1) wideband, high-performance metallic waveguide phase shifters to plug into a waveguide horn array for a relay satellite in geostationary orbit to track low Earth orbit satellites with maximum phase change rates of 5.1°/s to 45.4°/s, depending on the applied voltages, and (2) low-profile planar delay-line phase shifter stacks with very thin integrated MLC varactors for fast tuning, which are assembled into a multi-stack, flat-panel, beam-steering phased array, being able to scan the beam from −60° to +60° in about 10 ms. The loaded-line phase shifters have an insertion loss of about 3 dB at 30 GHz for a 400° differential phase shift and a figure-of-merit (FoM) > 120°/dB over a bandwidth of about 2.5 GHz. The critical switch-off response time to change the orientation of the microwave LCs from parallel to perpendicular with respect to the RF field (worst case), which corresponds to the time for 90 to 10% decay in the differential phase shift, is in the range of 30 ms for a LC layer height of about 4 µm. These MLC phase shifter stacks are fabricated in a standard Liquid Crystal Display (LCD) process for manufacturing low-cost large-scale ESAs, featuring single- and multiple-beam steering with very low power consumption, high linearity, and high power-handling capability. With a modular concept and hybrid analog/digital architecture, these smart antennas are flexible in size to meet the specific requirements for operating in satellite ground and user terminals, but also in 5G mm-wave systems. Full article

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm². TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode. Full article