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The inner spacer thickness (T_IS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T_IS variation (ΔT_IS). The gate length (L_G) depends on the T_IS. Thus, the DC/AC performance is significantly affected by ΔT_IS. Because the effects of ΔT_IS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔT_IS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (tr_pbt) should be considered with ΔT_IS because the gate controllability over tr_pbt is significantly dependent on ΔT_IS,B. If the S/D recess depth (T_SD) variation cannot be completely eliminated, reducing ΔT_IS,B is crucial for suppressing the effects of tr_pbt. It is noteworthy that reducing ΔT_IS,B is the most important factor when the T_SD variation occurs, whereas reducing ΔT_IS,T and ΔT_IS,M is crucial in the absence of T_SD variation to minimize the DC performance variation. As the T_IS increases, the gate capacitance (C_gg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of C_gg to each ΔT_IS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since T_SD of 5 nm increases the off-state current (I_off) sensitivity to ΔT_IS,B by a factor of 22.5 in NFETs, the ΔT_IS,B below 1 nm is essential for further scaling and yield enhancement. Full article