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Open AccessArticle

In-Pipeline Processor Protection against Soft Errors

by Ján Mach, Lukáš Kohútka and Pavel Čičák

J. Low Power Electron. Appl. 2023, 13(2), 33; https://doi.org/10.3390/jlpea13020033 - 10 May 2023

Cited by 6 | Viewed by 3955

The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%. Full article

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18 pages, 4281 KB

Open AccessArticle

Variable Delayed Dual-Core Lockstep (VDCLS) Processor for Safety and Security Applications

by Krzysztof Marcinek and Witold A. Pleskacz

Electronics 2023, 12(2), 464; https://doi.org/10.3390/electronics12020464 - 16 Jan 2023

Cited by 11 | Viewed by 7362

Abstract

Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications requiring functional safety. As the semiconductor process nodes keep shrinking, the DCLS technique is also more and more frequently seen in industrial or even consumer electronics. The paper presents the novel approach to the DCLS technique. While the typical approach is to set the slave core delay as a fixed number of clock cycles, we allow the checker core to run freely behind the main core within the constrained boundaries of clock cycles. This increases the temporal diversity needed for common mode failure mitigation. The system integrity provided by DCLS may also be used in the area of security applications. In this paper, we show that the proposed Variable Delayed Dual-Core Lockstep technique can flatten the power consumption correlation between the running cores, essential for a wide range of attacks. The proposed technique was implemented in the RISC-V processor core and verified in the Xilinx VCU108 FPGA platform. Full article

(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)

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