Search Results (5)

A grid-forming (GFM) inverter can effectively support active power and reactive power, and the stability problem induced by the low inertia can be thereby alleviated in a power electronics-dominated power system. Yet, the voltage source characteristic presented by the grid-forming inverter induces an overcurrent problem during a short-circuit fault. Furthermore, the time delay induces an inrush current in traditional digital control, triggered by a predefined timing sequence. To address the overcurrent problem of the GFM inverter controlled by the digital controller, the operation characteristics of GFM inverters under grid-voltage drops are investigated, and a mathematical model of the instantaneous fault current is established, which depicts the relationship between the instantaneous fault current’s magnitude, grid-voltage drop severity, equivalent output impedance, and current inner-loop response speed. Then, a Set–Reset (SR) latch-based dynamic current limitation with event-triggered control is proposed for the low-voltage ride-through of the GFM inverter. In the proposed method, the current limitation is enabled during grid fault, and the active and reactive powers can be recovered rapidly after fault clearance. Meanwhile, the active and reactive power references are designed to enhance synchronization stability during the grid fault. The proposed method addresses the issue of the repeated switching of virtual impedance during grid fault and achieves rapid power recovery after fault clearance. In addition, the proposed method uses the logic of event triggers to respond to the overcurrent event in real time and realize overcurrent protection. The simulation and experimental results demonstrate the effectiveness of the proposed method in current limitation and active-power recovery after fault clearance. Full article

A Surface-Riding Wave Energy Converter (SR-WEC) featuring a sliding magnet inside a pitching cylindrical hull is investigated as an easily deployable small power device to support small-scale marine operations. This study extends the earlier development of the system by authors to enhance power performance through the application of end spring and latching control. The inclusion of springs at the tube’s end enhances the magnet release and travel speeds as well as the average power output compared to systems without them. Further improvement of power output can also be achieved by employing optimal latching control. We introduced constant-angle and variable-angle unlatching strategies to determine optimal parameters in combination with passive and reactive power take-off (PTO) controls to assess their effectiveness. The optimized latching control and end spring can increase 60–80% more power output compared with the case without them under certain PTO damping. Additionally, we discussed the effects of limiting peak powers and associated energy leaks with latching. Full article

As a module of the internet of things (IOT) information security system, the true random number generator (TRNG) plays an important role in overall performance. In this paper, a low-power TRNG based on dual oscillators is proposed. Two high-frequency cross-coupled oscillators are used to generate high-jitter clock signals, and then the SR latch with power supply below standard power supply voltage is adopted to process the oscillator output to maintain its metastability and increase jitter. The circuit is realized by an SMIC 180 nm 1P6M mixed-signal process. The experimental results show that when power supply voltage is 1.8 V, the circuit outputs a random number bit rate of 200 kb/s, the core area is 0.0039 mm², and the power consumption is only 36 µw. The output random sequences can pass the NIST SP 800-22 test. Full article

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature. Full article

A random number generator (RNG), a cryptographic technology that plays an important role in security and sensor networks, can be designed using a linear feedback shift register (LFSR). This cryptographic transformation is currently done through CMOS. It has been developed by reducing the size of the gate and increasing the degree of integration, but it has reached the limit of integration due to the quantum tunneling phenomenon. Quantum-dot cellular automata (QCA), one of the quantum circuit design technologies to replace this, has superior performance compared to CMOS in most performance areas, such as space, speed, and power. Most of the LFSRs in QCA are designed as shift registers (SR), and most of the SR circuits proposed based on the existing QCA have a planar structure, so the cell area is large and the signal is unstable when a plane intersection is implemented. Therefore, in this paper, we propose a multilayered 2-to-1 QCA multiplexer and a D-latch, and we make blocks based on D-latch and connect these blocks to make SR. In addition, the LFSR structure is designed by adding an XOR operation to it, and we additionally propose an LFSR capable of dual-edge triggering. The proposed structures were completed with a very meticulous design technique to minimize area and latency using cell interaction, and they achieve high performance compared to many existing circuits. For the proposed structures, the cost and energy dissipation are calculated through simulation using QCADesigner and QCADesigner-E, and their efficiency is verified. Full article