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Keywords = DLL for automatic calibration

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16 pages, 7536 KB  
Article
A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process
by Fangyuan Xu, Xuan Guo, Zeyu Li, Hanbo Jia, Danyu Wu and Jin Wu
Electronics 2023, 12(4), 924; https://doi.org/10.3390/electronics12040924 - 12 Feb 2023
Cited by 5 | Viewed by 4259
Abstract
This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the [...] Read more.
This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step. Full article
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5 pages, 1046 KB  
Proceeding Paper
Excel-Based Tool for Automatic Calibration of Urban Drainage System Models
by Anatoli Vassiljev, Ivar Annus, Nils Kändler, Murel Truu, Katrin Kaur and Kristjan Suits
Environ. Sci. Proc. 2022, 21(1), 30; https://doi.org/10.3390/environsciproc2022021030 - 21 Oct 2022
Viewed by 1430
Abstract
Climate change and aging infrastructure are the main stressors for existing urban drainage systems (UDS), causing more frequent overloading. The locations of flooded areas and system behavior under different scenarios can be analyzed using calibrated SWMM5 models. This study presents the implementation of [...] Read more.
Climate change and aging infrastructure are the main stressors for existing urban drainage systems (UDS), causing more frequent overloading. The locations of flooded areas and system behavior under different scenarios can be analyzed using calibrated SWMM5 models. This study presents the implementation of an automatic calibration module designed for SWMM5. This module can be utilized for different types of drainage systems, including those that contain only impervious subareas, a mix of impervious and pervious subareas, as well systems that include natural ditches or channels. The latter are the most complex because, in this case, it is necessary to include the inflow of groundwater to the model. A dynamic link library (DLL) created by the authors enables automatic calibration of 21 parameters in SWMM5 in previously defined limits. The module enables calibrating up to five parameters simultaneously. This study presents different strategies for calibration, describes their limitations and possible solutions. Full article
(This article belongs to the Proceedings of EWaS5 International Conference: “Water Security and Safety Management: Emerging Threats or New Challenges? Moving from Therapy and Restoration to Prognosis and Prevention”)
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