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16 pages, 5406 KiB

Open AccessArticle

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

by Jing Kang, Fei Liu, Ya Hai and Yongshan Wang

Electronics 2023, 12(7), 1610; https://doi.org/10.3390/electronics12071610 - 29 Mar 2023

Viewed by 2834

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0

^{\circ}

output [...] Read more.

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output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13

μ

m CMOS process with a 0.072 mm

^{2}

core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps. Full article

(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)

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19 pages, 6783 KiB

Open AccessArticle

A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

by Jiyun Tong, Sha Wang, Shuang Zhang, Mengdi Zhang, Ye Zhao and Fazhan Zhao

Sensors 2022, 22(1), 284; https://doi.org/10.3390/s22010284 - 31 Dec 2021

Cited by 2 | Viewed by 3607

Abstract

This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm² and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies. Full article

(This article belongs to the Section Communications)

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