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14 pages, 3439 KiB

Open AccessArticle

Baseline Calibration Scheme Embedded in Single-Slope ADC for Gas Sensor Applications

by Jang-Su Hyeon and Hyeon-June Kim

Electronics 2024, 13(7), 1252; https://doi.org/10.3390/electronics13071252 - 28 Mar 2024

Cited by 1 | Viewed by 1687

This paper introduces a single-slope analog-to-digital converter (SS ADC) with an embedded digital baseline calibration scheme designed to improve the accuracy and reliability of gas sensor measurements. The proposed SS ADC effectively leverages an up/down counter mechanism to ensure stable signal extraction from gas sensors, despite variations in the baseline distribution. The proposed SS ADC initiates with a down counting operation to capture the initial output value of the gas sensor, which, after A/D conversion, is stored as a reference point for future readings. Subsequent gas sensor output values are derived by performing an up counting operation from this baseline reference. This approach allows for real-time correction of the baseline during the SS A/D conversion process, obviating the need for complex post-processing and baseline correction algorithms. The proposed SS ADC with the baseline calibration scheme was designed using a 0.18 μm standard CMOS process to confirm its feasibility. It demonstrated a signal-to-noise and distortion ratio (SNDR) of 57.56 dB and a spurious-free dynamic range (SFDR) of 59.02 dB, resulting in an effective number of bits (ENOB) of 9.27 bits in the post-simulation level. The proposed SS ADC has a total power consumption of 1.649 mW. This work offers an efficient solution to the baseline distribution problem in gas sensors, facilitating more reliable and accurate gas detection systems. Full article

(This article belongs to the Special Issue Analog and Mixed-Signal Circuit Designs and Their Applications)

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18 pages, 16777 KiB

Open AccessArticle

A 316MP, 120FPS, High Dynamic Range CMOS Image Sensor for Next Generation Immersive Displays

by Abhinav Agarwal, Jatin Hansrani, Sam Bagwell, Oleksandr Rytov, Varun Shah, Kai Ling Ong, Daniel Van Blerkom, Jonathan Bergey, Neil Kumar, Tim Lu, Deanan DaSilva, Michael Graae and David Dibble

Sensors 2023, 23(20), 8383; https://doi.org/10.3390/s23208383 - 11 Oct 2023

Cited by 6 | Viewed by 11193

Abstract

We present a 2D-stitched, 316MP, 120FPS, high dynamic range CMOS image sensor with 92 CML output ports operating at a cumulative date rate of 515 Gbit/s. The total die size is 9.92 cm × 8.31 cm and the chip is fabricated in a 65 nm, 4 metal BSI process with an overall power consumption of 23 W. A 4.3 µm dual-gain pixel has a high and low conversion gain full well of 6600e- and 41,000e-, respectively, with a total high gain temporal noise of 1.8e- achieving a composite dynamic range of 87 dB. Full article

(This article belongs to the Special Issue Special Issue on the 2023 International Image Sensor Workshop (IISW2023))

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