An FPGA Platform Proposal for Real-Time Acoustic Event Detection: Optimum Platform Implementation for Audio Recognition with Time Restrictions †
Abstract
:1. Introduction
2. Hardware Platforms Comparison
3. Hardware Proposal and Basic Algorithm Implementation
3.1. Platform Description
- Memory Control Blocks (MCB) to manage auxiliary DDR memories.
- Digital Clock Managers (DCMs) able to modify some aspects of the clock signals such as multiply or divide the input frequency; (ii) condition a clock; (iii) phase shift; (iv) eliminate clock skew and (v) mirror, forward, or rebuffer a clock Signal.
- Block RAMs to implement two independent 18 kbits RAM or one 36 kbits in Xilinx series 7 FPGA.
- A DSP block which include a pre-adder, multiplication and accumulator able to implement different functions of digital signal processing.
3.2. Algorithm Description
4. Conclusions
Author Contributions
Acknowledgments
Conflicts of Interest
Abbreviations
FPGA | Field Programmable Gate Array |
VHDL | VHSIC Hardware Description Language |
GTM | Grup de Recerca en Tecnologies Mèdia |
ARM | Advanced RISC Machines |
MCU | Microcontrollers |
DSP | Digital Signal Processor |
CLB | Configurable Logic Blocks |
MCB | Memory Control Blocks |
DCM | Digital Clock Managers |
GTCC | Gammatones Coefficients |
FFT | Fast Fourier Transform |
ROM | Read Only Memory |
RAM | Random Access Memory |
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FFT (ASM) | 24 MHz Cycle Count | 24 MHz Time (µs) | 48 MHz Cycle Count | 48 MHz Time (µs) | 72 MHz Cycle Count | 72 MHz Time (µs) |
---|---|---|---|---|---|---|
FFT-64 | 3847 | 160 | 4025 | 84 | 4764 | 66 |
FFT-256 | 21,039 | 876 | 22,176 | 462 | 26,065 | 362 |
FFT-1024 | 100,180 | 4174 | 102,057 | 2126 | 127,318 | 1768 |
FIR-32 | 3516 | 146.5 | 3525 | 73.4 | 3727 | 5176 |
Basys-3 | Slices | Logic Cells | Bloc RAM | DSPs | Price |
---|---|---|---|---|---|
XC7A35T-1CPG236C | 33,280 | 33,280 | 1800 kbit | 90 | 150 $ |
Basys-3 | LUT | FF | BRAM | DSP |
---|---|---|---|---|
FFT | 709 | 1385 | 4 | 4 |
48 Filter Banks | 0 | 0 | 48 | 0 |
Square Root | 783 | 0 | 0 | 0 |
Total | 7949 | 24,800 | 11 | 25 |
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Hervás, M.; Alsina-Pagès, R.M. An FPGA Platform Proposal for Real-Time Acoustic Event Detection: Optimum Platform Implementation for Audio Recognition with Time Restrictions. Proceedings 2017, 1, 2. https://doi.org/10.3390/ecsa-3-S2001
Hervás M, Alsina-Pagès RM. An FPGA Platform Proposal for Real-Time Acoustic Event Detection: Optimum Platform Implementation for Audio Recognition with Time Restrictions. Proceedings. 2017; 1(2):2. https://doi.org/10.3390/ecsa-3-S2001
Chicago/Turabian StyleHervás, Marcos, and Rosa Ma Alsina-Pagès. 2017. "An FPGA Platform Proposal for Real-Time Acoustic Event Detection: Optimum Platform Implementation for Audio Recognition with Time Restrictions" Proceedings 1, no. 2: 2. https://doi.org/10.3390/ecsa-3-S2001