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Open AccessEditor’s ChoiceArticle

A GNN-Based Placement Optimization Guidance Framework by Physical and Timing Prediction

by Peng Cao, Zhi Li and Wenjie Ding

Electronics 2025, 14(2), 329; https://doi.org/10.3390/electronics14020329 - 15 Jan 2025

Viewed by 1491

Placement is crucial in physical design flow with significant impact on later routability and ultimate manufacturability in terms of performance, power, and area (PPA), which may deviate from finding the optimal solution and/or lead to unnecessary iterations suffering from interleaved optimization steps and inaccurate PPA estimation. To solve this issue, we propose a physical- and timing-related placement optimization guidance framework which provides candidate gate sizing and buffer insertion solutions as well as a path group for potential violated paths based on graph neural networks (GNNs) to improve placement quality significantly and efficiently. Experimental results on the OpenCores benchmarks with 22 nm technology demonstrate that the proposed placement optimization guidance framework achieves up to 35.66% and 43.51% worst negative slack (WNS) and total negative slack (TNS) improvement and 52.17% reduction in the number of violating paths (NVP), which is beneficial to later routing stages with 2.33% wirelength decrease. Full article

(This article belongs to the Special Issue Innovations in Digital and Analog Electronic Systems for Next-Generation Devices)

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11 pages, 2761 KB

Open AccessArticle

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

by Mohammed Darmi, Lekbir Cherif, Jalal Benallal, Rachid Elgouri and Nabil Hmina

Electronics 2017, 6(4), 78; https://doi.org/10.3390/electronics6040078 - 4 Oct 2017

Cited by 9 | Viewed by 7936

Abstract

As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical designers and electronic design automation (EDA) providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR). An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP) technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS) and total negative slack (TNS) improved up to 13% and 56%, respectively, compared to the baseline flow. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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