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Open AccessEditor’s ChoiceArticle

High-Performance All-Optical Logic Gates Based on Silicon Racetrack and Microring Resonators

by Amer Kotb, Zhiyang Wang and Kyriakos E. Zoiros

Electronics 2025, 14(15), 2961; https://doi.org/10.3390/electronics14152961 - 24 Jul 2025

Cited by 2 | Viewed by 2698

We propose a high-speed all-optical logic gate design based on silicon racetrack and ring resonators patterned on a silica substrate. The architecture features racetrack resonators at both the input and output, with a central ring resonator enabling the required phase-sensitive interference for logic processing. Logic operations are achieved through the interplay of constructive and destructive interference induced by phase-shifted input beams. Using the finite-difference time-domain (FDTD) method in Lumerical software, we simulate and demonstrate seven fundamental Boolean logic functions, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, at an operating wavelength of 1.33 µm. The system supports a data rate of 47.94 Gb/s, suitable for ultrafast optical computing. The performance is quantitatively evaluated using the contrast ratio (CR) as the reference metric, with more than acceptable values of 13.09 dB (XOR), 13.84 dB (AND), 13.14 dB (OR), 13.80 dB (NOT), 14.53 dB (NOR), 13.80 dB (NAND), and 14.67 dB (XNOR), confirming strong logic level discrimination. Comparative analysis with existing optical gate designs underscores the advantages of our compact silicon-on-silica structure in terms of speed, CR performance, and integration potential. This study validates the effectiveness of racetrack–ring configurations for next-generation all-optical logic circuits. Full article

(This article belongs to the Special Issue Section Collection Series: Recent Advances in Optoelectronics from Lab to Industry, 2nd Edition)

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21 pages, 3080 KB

Open AccessArticle

RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

by Andrea Coluccio, Antonia Ieva, Fabrizio Riente, Massimo Ruo Roch, Marco Ottavi and Marco Vacca

Electronics 2022, 11(19), 2990; https://doi.org/10.3390/electronics11192990 - 21 Sep 2022

Cited by 5 | Viewed by 22206

Abstract

Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption. Full article

(This article belongs to the Special Issue Feature Papers in Computer Science & Engineering)

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14 pages, 4085 KB

Open AccessArticle

Manipulation of Skyrmion Motion Dynamics for Logical Device Application Mediated by Inhomogeneous Magnetic Anisotropy

by Jia-Qiang Lin, Ji-Pei Chen, Zhen-Yu Tan, Yuan Chen, Zhi-Feng Chen, Wen-An Li, Xing-Sen Gao and Jun-Ming Liu

Nanomaterials 2022, 12(2), 278; https://doi.org/10.3390/nano12020278 - 16 Jan 2022

Cited by 15 | Viewed by 3943

Abstract

Magnetic skyrmions are promising potential information carriers for future spintronic devices owing to their nanoscale size, non-volatility and high mobility. In this work, we demonstrate the controlled manipulation of skyrmion motion and its implementation in a new concept of racetrack logical device by introducing an inhomogeneous perpendicular magnetic anisotropy (PMA) via micromagnetic simulation. Here, the inhomogeneous PMA can be introduced by a capping nano-island that serves as a tunable potential barriers/well which can effectively modulate the size and shape of isolated skyrmion. Using the inhomogeneous PMA in skyrmion-based racetrack enables the manipulation of skyrmion motion behaviors, for instance, blocking, trapping or allowing passing the injected skyrmion. In addition, the skyrmion trapping operation can be further exploited in developing special designed racetrack devices with logic AND and NOT, wherein a set of logic AND operations can be realized via skyrmion–skyrmion repulsion between two skyrmions. These results indicate an effective method for tailoring the skyrmion structures and motion behaviors by using inhomogeneous PMA, which further provide a new pathway to all-electric skyrmion-based memory and logic devices. Full article

(This article belongs to the Special Issue Nano-Magnets and Nano-Magnetisms)

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