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18 pages, 750 KB  
Article
DTR-SHIELD: Mutual Synchronization for Protecting against DoS Attacks on the SHIELD Protocol with AES-CTR Mode
by Sang-su Lee, Jong-sik Moon, Yong-je Choi, Daewon Kim and Seungkwang Lee
Sensors 2024, 24(13), 4163; https://doi.org/10.3390/s24134163 - 26 Jun 2024
Cited by 2 | Viewed by 1996
Abstract
To enhance security in the semiconductor industry’s globalized production, the Defense Advanced Research Projects Agency (DARPA) proposed an authentication protocol under the Supply Chain Hardware Integrity for Electronics Defense (SHIELD) program. This protocol integrates a secure hardware root-of-trust, known as a dielet, into [...] Read more.
To enhance security in the semiconductor industry’s globalized production, the Defense Advanced Research Projects Agency (DARPA) proposed an authentication protocol under the Supply Chain Hardware Integrity for Electronics Defense (SHIELD) program. This protocol integrates a secure hardware root-of-trust, known as a dielet, into integrated circuits (ICs). The SHIELD protocol, combined with the Advanced Encryption Standard (AES) in counter mode, named CTR-SHIELD, targets try-and-check attacks. However, CTR-SHIELD is vulnerable to desynchronization attacks on its counter blocks. To counteract this, we introduce the DTR-SHIELD protocol, where DTR stands for double counters. DTR-SHIELD addresses the desynchronization issue by altering the counter incrementation process, which previously solely relied on truncated serial IDs. Our protocol adds a new AES encryption step and requires the dielet to transmit an additional 100 bits, ensuring more robust security through active server involvement and message verification. Full article
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13 pages, 2270 KB  
Perspective
Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging
by Zijin Pan, Xunyu Li, Weiquan Hao, Runyu Miao, Zijian Yue and Albert Wang
Electronics 2024, 13(12), 2341; https://doi.org/10.3390/electronics13122341 - 15 Jun 2024
Cited by 3 | Viewed by 6901
Abstract
Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond [...] Read more.
Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies. Full article
(This article belongs to the Special Issue Advanced Electronic Packaging Technology)
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