Special Issue "Selected Papers from IEEE S3S Conference 2013"

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (14 March 2014)

Special Issue Editors

Guest Editor
Prof. David Bol (Website)

ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Phone: +3210472539
Fax: +32 10472598
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Guest Editor
Dr. Steven A. Vitale

Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
Fax: 1 781 981 7889

Special Issue Information

Dear Colleagues,

For more than two decades, low-power consumption has been paramount for integrated circuits (ICs) and systems-on-a-chip (SoCs). In today’s sub-100 nm technologies,
low-power design flows are maturing with techniques, such as clock/power gating,
multi-Vt/Vdd assignment, and dynamic frequency/voltage scaling, becoming mainstream. However, further power savings are still needed for extremely power-constrained applications, such as green computing, mobile wireless communications, sensor networks, and biomedical devices. Feasible ways of achieving further power savings include, for example, sub-threshold and ultra-low-voltage operation, SOI technology and circuits, and 3-D and heterogeneous integration. In 2013, a new event gathered researchers studying the aforementioned three topics to share their views and advances regarding lower-power and more efficient ICs and SoCs: the IEEE Unified S3S (SOI-3D-SubVt) Conference. This conference comes from the unification of the IEEE SOI and Sub-Vt conferences.

This issue of JLPEA is the third special issue dedicated to selected papers from the IEEE S3S Conference 2013 held in Monterey, CA, on October 7-10, 2013. Extended versions of papers presented at the conference will be invited for submission to this special issue. A selection of the invited papers will be made based on their low-power content and their scientific/technical excellence.

Prof. David Bol
Dr. Steven A. Vitale
Guest Editors

Submission

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. Papers will be published continuously (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are refereed through a peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed Open Access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 300 CHF (Swiss Francs). English correction and/or formatting fees of 250 CHF (Swiss Francs) will be charged in certain cases for those articles accepted for publication that require extensive additional formatting and/or English corrections.


Keywords

  • ultra-low voltage circuits and design techniques
  • SOI-specific circuits and design techniques
  • SOI devices, processes, and technologies
  • 3-D and heterogeneous system integration
  • memory design and technologies
  • analog and RF technologies and circuits
  • implantable and handheld biomedical devices
  • transistor variability and mitigation
  • ultra-low-power computation
  • device and fabrication technology
  • energy harvesting techniques
  • unattended remote sensors

Published Papers (9 papers)

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Research

Jump to: Review

Open AccessArticle Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime
J. Low Power Electron. Appl. 2014, 4(3), 201-213; doi:10.3390/jlpea4030201
Received: 28 February 2014 / Revised: 27 June 2014 / Accepted: 8 July 2014 / Published: 16 July 2014
Cited by 2 | PDF Full-text (897 KB) | HTML Full-text | XML Full-text
Abstract
The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are [...] Read more.
The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the transconductance over drain current (gm/Id) method is preferable for variability studies. It is demonstrated that the subthreshold drain current variability in short channel devices cannot be described by threshold voltage variability. It is suggested to include the effective body factor incorporating short channel effects in order to properly model the subthreshold drain current variability. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability
J. Low Power Electron. Appl. 2014, 4(3), 188-200; doi:10.3390/jlpea4030188
Received: 28 February 2014 / Revised: 28 May 2014 / Accepted: 25 June 2014 / Published: 15 July 2014
Cited by 6 | PDF Full-text (1620 KB) | HTML Full-text | XML Full-text
Abstract
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is [...] Read more.
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials
J. Low Power Electron. Appl. 2014, 4(2), 153-167; doi:10.3390/jlpea4020153
Received: 28 February 2014 / Revised: 1 June 2014 / Accepted: 3 June 2014 / Published: 20 June 2014
Cited by 2 | PDF Full-text (1348 KB) | HTML Full-text | XML Full-text
Abstract
The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V [...] Read more.
The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle MOS Current Mode Logic Near Threshold Circuits
J. Low Power Electron. Appl. 2014, 4(2), 138-152; doi:10.3390/jlpea4020138
Received: 6 March 2014 / Revised: 29 April 2014 / Accepted: 15 May 2014 / Published: 11 June 2014
Cited by 1 | PDF Full-text (469 KB) | HTML Full-text | XML Full-text
Abstract
Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant [...] Read more.
Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs
J. Low Power Electron. Appl. 2014, 4(2), 110-118; doi:10.3390/jlpea4020110
Received: 28 February 2014 / Revised: 7 May 2014 / Accepted: 16 May 2014 / Published: 23 May 2014
PDF Full-text (859 KB) | HTML Full-text | XML Full-text
Abstract
A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved [...] Read more.
A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin). Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessArticle Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology
J. Low Power Electron. Appl. 2014, 4(2), 77-89; doi:10.3390/jlpea4020077
Received: 1 March 2014 / Revised: 22 April 2014 / Accepted: 23 April 2014 / Published: 5 May 2014
Cited by 5 | PDF Full-text (1113 KB) | HTML Full-text | XML Full-text
Abstract
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV [...] Read more.
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

Review

Jump to: Research

Open AccessReview Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level
J. Low Power Electron. Appl. 2014, 4(3), 168-187; doi:10.3390/jlpea4030168
Received: 14 March 2014 / Revised: 20 June 2014 / Accepted: 27 June 2014 / Published: 7 July 2014
PDF Full-text (1151 KB) | HTML Full-text | XML Full-text
Abstract
Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels [...] Read more.
Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Open AccessReview An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications
J. Low Power Electron. Appl. 2014, 4(2), 119-137; doi:10.3390/jlpea4020119
Received: 1 March 2014 / Revised: 6 May 2014 / Accepted: 19 May 2014 / Published: 27 May 2014
Cited by 1 | PDF Full-text (1198 KB) | HTML Full-text | XML Full-text
Abstract
Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work [...] Read more.
Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Figures

Open AccessReview Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V
J. Low Power Electron. Appl. 2014, 4(2), 65-76; doi:10.3390/jlpea4020065
Received: 27 February 2014 / Revised: 7 April 2014 / Accepted: 10 April 2014 / Published: 24 April 2014
Cited by 4 | PDF Full-text (441 KB) | HTML Full-text | XML Full-text
Abstract
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many [...] Read more.
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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