J. Low Power Electron. Appl. 2014, 4(2), 65-76; doi:10.3390/jlpea4020065

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

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Received: 27 February 2014; in revised form: 7 April 2014 / Accepted: 10 April 2014 / Published: 24 April 2014
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract: Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era.
Keywords: ultralow power; ultralow voltage; CMOS; minimum energy point; variability; back bias; FDSOI; silicon-on-thin-buried-oxide (SOTB); thin BOX
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MDPI and ACS Style

Sugii, N.; Yamamoto, Y.; Makiyama, H.; Yamashita, T.; Oda, H.; Kamohara, S.; Yamaguchi, Y.; Ishibashi, K.; Mizutani, T.; Hiramoto, T. Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V. J. Low Power Electron. Appl. 2014, 4, 65-76.

AMA Style

Sugii N, Yamamoto Y, Makiyama H, Yamashita T, Oda H, Kamohara S, Yamaguchi Y, Ishibashi K, Mizutani T, Hiramoto T. Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V. Journal of Low Power Electronics and Applications. 2014; 4(2):65-76.

Chicago/Turabian Style

Sugii, Nobuyuki; Yamamoto, Yoshiki; Makiyama, Hideki; Yamashita, Tomohiro; Oda, Hidekazu; Kamohara, Shiro; Yamaguchi, Yasuo; Ishibashi, Koichiro; Mizutani, Tomoko; Hiramoto, Toshiro. 2014. "Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V." J. Low Power Electron. Appl. 4, no. 2: 65-76.

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