J. Low Power Electron. Appl. 2014, 4(3), 188-200; doi:10.3390/jlpea4030188
Article

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

1,* email, 1email, 2email, 1email, 1email, 1email, 3email and 1email
Received: 28 February 2014; in revised form: 28 May 2014 / Accepted: 25 June 2014 / Published: 15 July 2014
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract: Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.
Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)
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MDPI and ACS Style

Hioki, M.; Ma, C.; Kawanami, T.; Ogasahara, Y.; Nakagawa, T.; Sekigawa, T.; Tsutsumi, T.; Koike, H. SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability. J. Low Power Electron. Appl. 2014, 4, 188-200.

AMA Style

Hioki M, Ma C, Kawanami T, Ogasahara Y, Nakagawa T, Sekigawa T, Tsutsumi T, Koike H. SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability. Journal of Low Power Electronics and Applications. 2014; 4(3):188-200.

Chicago/Turabian Style

Hioki, Masakazu; Ma, Chao; Kawanami, Takashi; Ogasahara, Yasuhiro; Nakagawa, Tadashi; Sekigawa, Toshihiro; Tsutsumi, Toshiyuki; Koike, Hanpei. 2014. "SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability." J. Low Power Electron. Appl. 4, no. 3: 188-200.

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