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J. Low Power Electron. Appl. 2014, 4(3), 188-200; doi:10.3390/jlpea4030188
Article

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

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1 Electroinformatics Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan 2 Department of Information and Computer Science, College of Engineering, Kanazawa Institute of Technology, 7-1 Ohgigaoka, Nonoichi, Ishikawa 921-8501, Japan 3 Computer Science Course, Fundamental Science and Technology, Graduate School of Science and Technology, Meiji University, 1-1-1 Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa 214-8571, Japan
This is an extended version of paper that was presented at the IEEE S3S Conference 2013.
* Author to whom correspondence should be addressed.
Received: 28 February 2014 / Revised: 28 May 2014 / Accepted: 25 June 2014 / Published: 15 July 2014
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
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Abstract

Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.
Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB) field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Hioki, M.; Ma, C.; Kawanami, T.; Ogasahara, Y.; Nakagawa, T.; Sekigawa, T.; Tsutsumi, T.; Koike, H. SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability. J. Low Power Electron. Appl. 2014, 4, 188-200.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert