Special Issue "Selected Papers from SubVt 2012 Conference"

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (1 February 2013)

Special Issue Editors

Guest Editor
Prof. David Bol (Website)

ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Phone: +3210472539
Fax: +32 10472598
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Guest Editor
Dr. Steven A. Vitale

Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
Fax: 1 781 981 7889

Special Issue Information

Dear Colleagues,

Ultra-low-voltage circuits operating in the near- or sub-threshold region offer invaluable power savings for ultra-low-power applications. However, designers face significant challenges fighting against magnified sensitivity to process and temperature variations, low drain currents, high gate delay and higher proportion of leakage currents. This issue of JLPEA is the second special issue dedicated to selected papers from the Subthreshold Microelectronics Conference (SubVt 2012) held in Waltham, MA, on 9-10 October 2012. Extended versions of outstanding papers presented at SubVt 2012 are solicited for submission to this special issue but other works related to ultra-low-power microelectronics will also be considered.

Prof. David Bol
Dr. Steven A. Vitale
Guest Editors

Submission

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. Papers will be published continuously (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are refereed through a peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed Open Access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 300 CHF (Swiss Francs). English correction and/or formatting fees of 250 CHF (Swiss Francs) will be charged in certain cases for those articles accepted for publication that require extensive additional formatting and/or English corrections.

About Copyright

Upon publication in JLPEA, authors are requested to acquire reprint permissions for the IEEE copyrighted materials they want use without significant modifications. If less than 50% of each paper is reused and the papers are sufficiently revised, permissions will be granted to the authors as long as the following requirements are fulfilled:

  • Senior author's approval of the revisions is obtained, that the following IEEE credit/copyright notice appears prominently on the first page of the reprinted material, with the appropriate details filled in:

Based on "(full paper title)", by (authors' names) which appeared in (complete publication information).   © [Year] IEEE.

  • A new title is used for the new paper (extended version of the IEEE conference paper), to indicate that the paper has been substantially revised.

Keywords

Research and review papers on subthreshold microelectronics are solicited in areas including, but not limited to:

  • ultra-low voltage logic circuits and techniques
  • memory design and technologies
  • unattended remote sensors
  • memory technologies
  • radiation effects
  • implantable and handheld biomedical devices
  • transistor variability and mitigation
  • energy harvesting techniques
  • ultra-low-power computation
  • asynchronous circuits
  • analog and RF technologies and circuits
  • device and fabrication technology

Published Papers (8 papers)

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Research

Jump to: Review

Open AccessArticle Sub-Threshold Standard Cell Sizing Methodology and Library Comparison
J. Low Power Electron. Appl. 2013, 3(3), 233-249; doi:10.3390/jlpea3030233
Received: 4 February 2013 / Revised: 29 May 2013 / Accepted: 25 June 2013 / Published: 15 July 2013
Cited by 2 | PDF Full-text (453 KB) | HTML Full-text | XML Full-text
Abstract
Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold [...] Read more.
Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of [1,2] on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this paper, the equivalent N and P networks are derived based on the best and worst case transition times. The slack available in the best-case timing arc is reduced by using smaller transistors on that path, while the timing of the worst-case timing arc is improved by using bigger transistors. The optimization is done such that the overall area remains constant with regard to the area before optimization. Two sizing styles are applied, one is based on both transistor width and length tuning, and the other one is based on width tuning only. Compared to super-threshold libraries, at 0.3 V, the proposed libraries achieve 49% and 89% average cell timing improvement and 55% and 31% power delay product improvement at 40 nm and 90 nm respectively. From ITC (International Test Conference 99) benchmark circuit synthesis results, at 0.3 V the proposed library achieves up to 52% timing improvement and 53% power savings in the 40 nm technology node. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessArticle Bias-Flip Technique for Frequency Tuning of Piezo-Electric Energy Harvesting Devices
J. Low Power Electron. Appl. 2013, 3(2), 194-214; doi:10.3390/jlpea3020194
Received: 13 March 2013 / Revised: 7 May 2013 / Accepted: 24 May 2013 / Published: 18 June 2013
Cited by 2 | PDF Full-text (476 KB) | HTML Full-text | XML Full-text
Abstract
Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. Manufacturing tolerances make it difficult to match the Energy Harvesting Device [...] Read more.
Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. Manufacturing tolerances make it difficult to match the Energy Harvesting Device (EHD) resonant frequency to the source vibration frequency, and the source vibration frequency may vary with time. Previous work has recognized that it is possible to tune the resonant frequency of an EHD using a tunable, reactive impedance at the output of the device. The present paper develops the theory of electrical tuning, and proposes the Bias-Flip (BF) technique, to implement this tunable, reactive impedance. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessArticle A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers
J. Low Power Electron. Appl. 2013, 3(2), 159-173; doi:10.3390/jlpea3020159
Received: 13 February 2013 / Revised: 8 April 2013 / Accepted: 25 April 2013 / Published: 24 May 2013
PDF Full-text (845 KB) | HTML Full-text | XML Full-text
Abstract
Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased [...] Read more.
Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking. The circuit enables flexible tuning of the offset voltage. Measurements taken from a 45 nm test chip show the circuit is able to limit the offset to 20 mV. A 16kB SRAM is designed using the auto-zeroing circuit for the sense amps. The reduction in the total read energy and delay is reported for various configurations of the memory. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessArticle Reconfigurable Threshold Logic Gates using Memristive Devices
J. Low Power Electron. Appl. 2013, 3(2), 174-193; doi:10.3390/jlpea3020174
Received: 4 February 2013 / Revised: 4 April 2013 / Accepted: 25 April 2013 / Published: 24 May 2013
Cited by 3 | PDF Full-text (7644 KB) | HTML Full-text | XML Full-text
Abstract
We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been [...] Read more.
We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in discrete hardware using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessArticle Low Power Dendritic Computation for Wordspotting
J. Low Power Electron. Appl. 2013, 3(2), 73-98; doi:10.3390/jlpea3020073
Received: 6 February 2013 / Revised: 7 April 2013 / Accepted: 19 April 2013 / Published: 21 May 2013
Cited by 7 | PDF Full-text (1436 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we demonstrate how a network of dendrites can be used to build the state decoding block of a wordspotter similar to a Hidden Markov Model (HMM) classifier structure. We present simulation and experimental data for a single line dendrite [...] Read more.
In this paper, we demonstrate how a network of dendrites can be used to build the state decoding block of a wordspotter similar to a Hidden Markov Model (HMM) classifier structure. We present simulation and experimental data for a single line dendrite and also experimental results for a dendrite-based classifier structure. This work builds on previously demonstrated building blocks of a neural network: the channel, synapses and dendrites using CMOS circuits. These structures can be used for speech and pattern recognition. The computational efficiency of such a system is >10 MMACs/μW as compared to Digital Systems which perform 10 MMACs/mW. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessArticle Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling
J. Low Power Electron. Appl. 2013, 3(2), 54-72; doi:10.3390/jlpea3020054
Received: 4 February 2013 / Revised: 16 March 2013 / Accepted: 19 March 2013 / Published: 29 April 2013
Cited by 6 | PDF Full-text (3640 KB) | HTML Full-text | XML Full-text
Abstract
Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and [...] Read more.
Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)

Review

Jump to: Research

Open AccessReview Exploration of Charge Recycling DC-DC Conversion Using a Switched Capacitor Regulator
J. Low Power Electron. Appl. 2013, 3(3), 250-266; doi:10.3390/jlpea3030250
Received: 6 January 2013 / Revised: 5 July 2013 / Accepted: 9 July 2013 / Published: 29 July 2013
PDF Full-text (492 KB) | HTML Full-text | XML Full-text
Abstract
The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. [...] Read more.
The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. The idea is to supply nominal (high) off-chip voltage to the cores which are then “voltage-stacked” to generate the near-threshold (low) voltages based on Kirchhoff’s voltage law through charge recycling. However, the effectiveness of this implicit down-conversion is affected by the current imbalance among the cores. The paper presents a design methodology and optimization strategy for highly efficient charge recycling on-chip regulation using a push-pull switched capacitor (SC) circuit. A dual-boundary hysteretic feedback control circuit has been designed for stacked loads. A stacked-voltage domain with its self-regulation capability combined with a SC converter has shown average efficiency of 78%–93% for 2:1 down-conversion with ILoad (max) of 200 mA and workload imbalance varying from 0–100%. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessReview A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications
J. Low Power Electron. Appl. 2013, 3(3), 215-232; doi:10.3390/jlpea3030215
Received: 18 March 2013 / Revised: 1 June 2013 / Accepted: 5 June 2013 / Published: 24 June 2013
Cited by 2 | PDF Full-text (740 KB) | HTML Full-text | XML Full-text
Abstract
This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and [...] Read more.
This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)

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