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J. Low Power Electron. Appl. 2014, 4(2), 77-89; doi:10.3390/jlpea4020077

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

IBM Corporation Systems and Technology Group, Hopewell Junction, NY 12533, USA
IBM Corporation Systems and Technology Group, Albany, NY 12203, USA
Formerly with IBM Corporation Systems and Technology Group
Conference version published in IEEE-S3S, 2013.
Author to whom correspondence should be addressed.
Received: 1 March 2014 / Revised: 22 April 2014 / Accepted: 23 April 2014 / Published: 5 May 2014
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
View Full-Text   |   Download PDF [1113 KB, uploaded 5 May 2014]   |  


For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation. View Full-Text
Keywords: EDRAM; 3D; SOI; through-silicon-via (TSV); wafer stacking EDRAM; 3D; SOI; through-silicon-via (TSV); wafer stacking

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This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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Batra, P.; Skordas, S.; LaTulipe, D.; Winstel, K.; Kothandaraman, C.; Himmel, B.; Maier, G.; He, B.; Gamage, D.W.; Golz, J.; Lin, W.; Vo, T.; Priyadarshini, D.; Hubbard, A.; Cauffman, K.; Peethala, B.; Barth, J.; Kirihata, T.; Graves-Abe, T.; Robson, N.; Iyer, S. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology. J. Low Power Electron. Appl. 2014, 4, 77-89.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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