http://www.mdpi.com/journal/jlpea Latest open access articles published in J. Low Power Electron. Appl. at http://www.mdpi.com/journal/jlpea http://www.mdpi.com/2079-9268/3/2/194 Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. Manufacturing tolerances make it difficult to match the Energy Harvesting Device (EHD) resonant frequency to the source vibration frequency, and the source vibration frequency may vary with time. Previous work has recognized that it is possible to tune the resonant frequency of an EHD using a tunable, reactive impedance at the output of the device. The present paper develops the theory of electrical tuning, and proposes the Bias-Flip (BF) technique, to implement this tunable, reactive impedance. Journal of Low Power Electronics and Applications 2013-06-18 3 2 Article 10.3390/jlpea3020194 194 214 2079-9268 2013-06-18 doi: 10.3390/jlpea3020194 Jianying Zhao Yogesh Ramadass Jeffrey Lang Jianguo Ma Dennis Buss http://www.mdpi.com/2079-9268/3/2/174 We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in discrete hardware using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Article 10.3390/jlpea3020174 174 193 2079-9268 2013-05-24 doi: 10.3390/jlpea3020174 Adrian Rothenbuhler Thanh Tran Elisa Smith Vishal Saxena Kristy Campbell http://www.mdpi.com/2079-9268/3/2/159 Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking. The circuit enables flexible tuning of the offset voltage. Measurements taken from a 45 nm test chip show the circuit is able to limit the offset to 20 mV. A 16kB SRAM is designed using the auto-zeroing circuit for the sense amps. The reduction in the total read energy and delay is reported for various configurations of the memory. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Article 10.3390/jlpea3020159 159 173 2079-9268 2013-05-24 doi: 10.3390/jlpea3020159 Peter Beshay Joseph Ryan Benton Calhoun http://www.mdpi.com/2079-9268/3/2/114 This paper presents the concept, structural design and implementation of components of a multifunctional sensory network, consisting of a Mobile Robotic Platform (MRP) and stationary multifunctional sensors, which are wirelessly communicating with the MRP. Each section provides the review of the principles of operation and the network components’ practical implementation. The analysis is focused on the structure of the robotic platform, sensory network and electronics and on the methods of the environment monitoring and data processing algorithms that provide maximal reliability, flexibility and stable operability of the system. The main aim of this project is the development of the Robotic Nurse (RN)—a 24/7 robotic helper for the hospital nurse personnel. To support long-lasting autonomic operation of the platform, all mechanical, electronic and photonic components were designed to provide minimal weight, size and power consumption, while still providing high operational efficiency, accuracy of measurements and adequateness of the sensor response. The stationary sensors serve as the remote “eyes, ears and noses” of the main MRP. After data acquisition, processing and analysing, the robot activates the mobile platform or specific sensors and cameras. The cross-use of data received from sensors of different types provides high reliability of the system. The key RN capabilities are simultaneous monitoring of physical conditions of a large number of patients and alarming in case of an emergency. The robotic platform Nav-2 exploits innovative principles of any-direction motion with omni-wheels, navigation and environment analysis. It includes an innovative mini-laser, the absorption spectrum analyser and a portable, extremely high signal-to-noise ratio spectrometer with two-dimensional detector array. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Review 10.3390/jlpea3020114 114 158 2079-9268 2013-05-24 doi: 10.3390/jlpea3020114 Igor Peshko Romuald Pawluczyk Dale Wick http://www.mdpi.com/2079-9268/3/2/99 This paper presents a compact structure of recursive discrete Fourier transform (RDFT) with prime factor (PF) and common factor (CF) algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051) and 11.5 (or 0.1176) mW at 25 (or 0.273) MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Article 10.3390/jlpea3020099 99 113 2079-9268 2013-05-24 doi: 10.3390/jlpea3020099 Shin-Chi Lai Yueh-Shu Lee Sheau-Fang Lei http://www.mdpi.com/2079-9268/3/2/73 In this paper, we demonstrate how a network of dendrites can be used to build the state decoding block of a wordspotter similar to a Hidden Markov Model (HMM) classifier structure. We present simulation and experimental data for a single line dendrite and also experimental results for a dendrite-based classifier structure. This work builds on previously demonstrated building blocks of a neural network: the channel, synapses and dendrites using CMOS circuits. These structures can be used for speech and pattern recognition. The computational efficiency of such a system is >10 MMACs/μW as compared to Digital Systems which perform 10 MMACs/mW. Journal of Low Power Electronics and Applications 2013-05-21 3 2 Article 10.3390/jlpea3020073 73 98 2079-9268 2013-05-21 doi: 10.3390/jlpea3020073 Suma George Jennifer Hasler Scott Koziol Stephen Nease Shubha Ramakrishnan http://www.mdpi.com/2079-9268/3/2/54 Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz. Journal of Low Power Electronics and Applications 2013-04-29 3 2 Article 10.3390/jlpea3020054 54 72 2079-9268 2013-04-29 doi: 10.3390/jlpea3020054 Pascal Meinerzhagen Adam Teman Robert Giterman Andreas Burg Alexander Fish http://www.mdpi.com/2079-9268/3/1/27 Usually Wide Dynamic Range (WDR) sensors that autonomously adjust their integration time to fit intra-scene illumination levels use a separate digital memory unit. This memory contains the data needed for the dynamic range. Motivated by the demands for low power and chip area reduction, we propose a different implementation of the aforementioned WDR algorithm by replacing the external digital memory with an analog in-pixel memory. This memory holds the effective integration time represented by analog encoding voltage (AEV). In addition, we present a “ranging” scheme of configuring the pixel integration time in which the effective integration time is configured at the first half of the frame. This enables a substantial simplification of the pixel control during the rest of the frame and thus allows for a significantly more remarkable DR extension. Furthermore, we present the implementation of “ranging” and AEV concepts on two different designs, which are targeted to reach five and eight decades of DR, respectively. We describe in detail the operation of both systems and provide the post-layout simulation results for the second solution. The simulations show that the second design reaches DR up to 170 dBs. We also provide a comparative analysis in terms of the number of operations per pixel required by our solution and by other widespread WDR algorithms. Based on the calculated results, we conclude that the proposed two designs, using “ranging” and AEV concepts, are attractive, since they obtain a wide dynamic range at high operation speed and low power consumption. Journal of Low Power Electronics and Applications 2013-03-22 3 1 Article 10.3390/jlpea3010027 27 53 2079-9268 2013-03-22 doi: 10.3390/jlpea3010027 Arthur Spivak Alexander Belenky Alexander Fish Orly Yadid-Pecht http://www.mdpi.com/2079-9268/3/1/9 This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS) process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range. Journal of Low Power Electronics and Applications 2013-02-28 3 1 Article 10.3390/jlpea3010009 9 26 2079-9268 2013-02-28 doi: 10.3390/jlpea3010009 Naser Khosro Pour François Krummenacher Maher Kayal http://www.mdpi.com/2079-9268/3/1/1 Loop control is an essential area of electronics engineering that today’s professionals need to master. Rather than delving into extensive theory, this practical book focuses on what you really need to know for compensating or stabilizing a given control system. You can turn instantly to practical sections with numerous design examples and ready-made formulas to help you with your projects in the field. You also find coverage of the underpinnings and principles of control loops so you can gain a more complete understanding of the material. This authoritative volume explains how to conduct analysis of control systems and provides extensive details on practical compensators. It helps you measure your system, showing how to verify if a prototype is stable and features enough design margin. Moreover, you learn how to secure high-volume production by bench-verified safety margins. Journal of Low Power Electronics and Applications 2013-01-24 3 1 New Book Received 10.3390/jlpea3010001 1 8 2079-9268 2013-01-24 doi: 10.3390/jlpea3010001 Shu-Kun Lin http://www.mdpi.com/2079-9268/2/4/282 This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire. Journal of Low Power Electronics and Applications 2012-12-12 2 4 Article 10.3390/jlpea2040282 282 300 2079-9268 2012-12-12 doi: 10.3390/jlpea2040282 Chien-Yu Lu Ching-Te Chuang http://www.mdpi.com/2079-9268/2/4/265 This paper reviews the direct connection of sensors to microcontrollers without using any analogue circuit (such as an amplifier or analogue-to-digital converter) in the signal path, thus resulting in a low-cost, lower-power sensor electronic interface. It first discusses the operating principle and explains how resistive and capacitive sensors with different topologies (i.e., single, differential and bridge type) can be directly connected to a microcontroller to build the so-called direct interface circuit. It then shows some applications of the proposed circuits using commercial devices and discusses their performance. Finally, it deals with the power consumption and proposes some design guidelines to reduce the current consumption of such circuits in active mode. Journal of Low Power Electronics and Applications 2012-11-29 2 4 Review 10.3390/jlpea2040265 265 281 2079-9268 2012-11-29 doi: 10.3390/jlpea2040265 Ferran Reverter http://www.mdpi.com/2079-9268/2/4/242 A low power adaptive digital baseband architecture is presented for a low-IF receiver of IEEE 802.15.4-2006. The digital section’s sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle the worst case conditions. We show that in a 0.13 μm CMOS technology, for an adaptive digital baseband section of the receiver, power saving can be up to 85% (0.49mW against 3.3mW) in favorable interference and signal conditions. The proposed concepts in the design are tested using a receiver test setup where the design is hosted on a FPGA. Journal of Low Power Electronics and Applications 2012-10-23 2 4 Abstract 10.3390/jlpea2040242 242 264 2079-9268 2012-10-23 doi: 10.3390/jlpea2040242 Satyam Dwivedi Bharadwaj Amrutur Navakanta Bhat http://www.mdpi.com/2079-9268/2/4/211 This paper reports a multi-channel neural spike recording system-on-chip with digital data compression and wireless telemetry. The circuit consists of 16 amplifiers, an analog time-division multiplexer, a single 8 bit analog-to-digital converter, a digital signal compression unit and a wireless transmitter. Although only 16 amplifiers are integrated in our current die version, the whole system is designed to work with 64, demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. Compression of the raw data is achieved by detecting the action potentials (APs) and storing 20 samples for each spike waveform. This compression method retains sufficiently high data quality to allow for single neuron identification (spike sorting). The 400 MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way, a 1:25 Mbit/s data rate is delivered within a limited band of about 3 MHz. The chip is realized in a 0:35 µm AMS CMOS process featuring a 3 V power supply with an area of 3:1 x 2:7 mm2. The achieved transmission range is over 10 m with an overall power consumption for 64 channels of 17:2 mW. This figure translates into a power budget of 269 µW per channel, in line with published results but allowing a larger transmission distance and more efficient bandwidth occupation of the wireless link. The integrated circuit was mounted on a small and light board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries, the system can continuously work for more than 100 hours allowing for long-lasting neural spike recordings. Journal of Low Power Electronics and Applications 2012-09-28 2 4 Article 10.3390/jlpea2040211 211 241 2079-9268 2012-09-28 doi: 10.3390/jlpea2040211 Andrea Bonfanti Maria Ceravolo Guido Zambra Riccardo Gusmeroli Gytis Baranauskas Gian Nicola Angotzi Alessandro Vato Emma Maggiolini Marianna Semprini Alessandro Sottocornola Spinelli Andrea Leonardo Lacaita http://www.mdpi.com/2079-9268/2/4/210 We have found the following error in the title of this article which was recently published in J. Low Power Electron. Appl. [...] Journal of Low Power Electronics and Applications 2012-09-26 2 4 Correction 10.3390/jlpea2040210 210 210 2079-9268 2012-09-26 doi: 10.3390/jlpea2040210 Ameet Chavan Praveen Palakurthi Eric MacDonald Joseph Neff Eric Bozeman http://www.mdpi.com/2079-9268/2/3/197 A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level. Journal of Low Power Electronics and Applications 2012-07-26 2 3 Article 10.3390/jlpea2030197 197 209 2079-9268 2012-07-26 doi: 10.3390/jlpea2030197 Sakkarapani Balagopal Vishal Saxena http://www.mdpi.com/2079-9268/2/2/180 This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV. Journal of Low Power Electronics and Applications 2012-06-06 2 2 Article 10.3390/jlpea2020180 180 196 2079-9268 2012-06-06 doi: 10.3390/jlpea2020180 Jani Mäkipää Matthew J. Turnquist Erkka Laulainen Lauri Koskinen http://www.mdpi.com/2079-9268/2/2/168 A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( < Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%. Journal of Low Power Electronics and Applications 2012-05-24 2 2 Article 10.3390/jlpea2020168 168 179 2079-9268 2012-05-24 doi: 10.3390/jlpea2020168 Ameet Chavan Praveen Palakurthi Eric MacDonald Joseph Neff Eric Bozeman http://www.mdpi.com/2079-9268/2/2/155 We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design. Journal of Low Power Electronics and Applications 2012-05-18 2 2 Article 10.3390/jlpea2020155 155 167 2079-9268 2012-05-18 doi: 10.3390/jlpea2020155 Piotr Olejarz Kyoungchul Park Samuel MacNaughton Mehmet R. Dokmeci Sameer Sonkusale http://www.mdpi.com/2079-9268/2/2/143 The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write VMIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4–13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the unassisted test case. Journal of Low Power Electronics and Applications 2012-04-18 2 2 Review 10.3390/jlpea2020143 143 154 2079-9268 2012-04-18 doi: 10.3390/jlpea2020143 James Boley Jiajing Wang Benton H. Calhoun http://www.mdpi.com/2079-9268/2/2/127 A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α† = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α† = 4.5958 for an 8% reduction in total power (PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy. Journal of Low Power Electronics and Applications 2012-03-29 2 2 Article 10.3390/jlpea2020127 127 142 2079-9268 2012-03-29 doi: 10.3390/jlpea2020127 Amila Edirisuriya Arjuna Madanayake Vassil S. Dimitrov Renato J. Cintra Jithra Adikari http://www.mdpi.com/2079-9268/2/1/98 Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A complete analysis of an advanced encryption standard (AES) S-box is conducted using a low-power (LP) 65 nm CMOS technology node. Measurements show that the DDSLL S-box has 35% less power consumption than the static CMOS S-box, with an area increase of only 12%, at the expense of a 2.5× increase in delay which remains fairly acceptable for low-power applications such as RFIDs and smart cards. Also when compared to other dynamic differential logic (DDL) styles, simulation results show that DDSLL and dynamic current mode logic (DyCML) consume the same power which is about 1.8× less that of sense amplifier based logic (SABL). The effect of process variations is also studied, measurement results show that the DDSLL style has lower variability in terms of dynamic power as the activity factor (αF) is deterministic thanks to glitch-free operation. As for security, the perceived information metric demonstrates that the DDSLL S-box has a 3× security margin compared to static CMOS. Therefore, DDSLL presents an interesting tradeoff between improved security and area constrained low-power designs. Journal of Low Power Electronics and Applications 2012-03-16 2 1 Article 10.3390/jlpea2010098 98 126 2079-9268 2012-03-16 doi: 10.3390/jlpea2010098 Dina Kamel Mathieu Renauld David Bol François-Xavier Standaert Denis Flandre http://www.mdpi.com/2079-9268/2/1/79 One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the development of low power consumption computing systems. In this paper we present one possible solution involving micro projection device based upon lasers and a digital light processing (DLP) matrix which is a matrix of electrically controllable mirrors capable of translating electrical signal to a time varying projected image. It can serve to substitute a screen and consume ten times less power than a conventional screen. The described device is a multifunctional highly efficient customized DLP light engine being capable of serving as an image projector and simultaneously to support range and topography estimation measurements. Journal of Low Power Electronics and Applications 2012-03-05 2 1 Article 10.3390/jlpea2010079 79 97 2079-9268 2012-03-05 doi: 10.3390/jlpea2010079 Yuval Kapellner Zeev Zalevsky http://www.mdpi.com/2079-9268/2/1/69 In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic power (PSC/Pdyn) while changing the design process. The analysis shows that the PSC/Pdyn ratio can increase significantly if the VT/Vdd ratio in new process decreases. An analytical expression is also derived for estimation of potential SC power reduction in MTCMOS processes by replacing low-VT transistors by high-VT devices in the same process. The proposed technique allows significant reduction of SC power without the need for process shift. The simulation results show good correlation with the analytical estimation at cell level, while demonstrating an average SC power saving of 36%. The performance impact is also validated, showing that timing degradation is minor and controllable. The proposed optimization technique is applicable to any multi-threshold process. The technique is simple for implementation, and can be easily integrated in the existing optimization tools. Journal of Low Power Electronics and Applications 2012-03-01 2 1 Article 10.3390/jlpea2010069 69 78 2079-9268 2012-03-01 doi: 10.3390/jlpea2010069 Arkadiy Morgenshtein http://www.mdpi.com/2079-9268/2/1/30 Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs). While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9 instruction set enabling them to run a full operating system software stack, and hence a wide variety of benchmarking applications. Journal of Low Power Electronics and Applications 2012-02-01 2 1 Article 10.3390/jlpea2010030 30 68 2079-9268 2012-02-01 doi: 10.3390/jlpea2010030 Kushal Datta Arindam Mukherjee Guangyi Cao Rohith Tenneti Vinay Vijendra Kumar Lakshmi Arun Ravindran Bharat S. Joshi http://www.mdpi.com/2079-9268/2/1/1 Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed. Journal of Low Power Electronics and Applications 2012-01-27 2 1 Review 10.3390/jlpea2010001 1 29 2079-9268 2012-01-27 doi: 10.3390/jlpea2010001 Eitan N. Shauly http://www.mdpi.com/2079-9268/1/3/357 Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to achieve comprehensive testing of low power designs and reduce test power consumption during test application. Journal of Low Power Electronics and Applications 2011-12-09 1 3 Article 10.3390/jlpea1030357 357 372 2079-9268 2011-12-09 doi: 10.3390/jlpea1030357 Xijiang Lin http://www.mdpi.com/2079-9268/1/3/334 While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well. Journal of Low Power Electronics and Applications 2011-10-11 1 3 Article 10.3390/jlpea1030334 334 356 2079-9268 2011-10-11 doi: 10.3390/jlpea1030334 Joseph Crop Evgeni Krimer Nariman Moezzi-Madani Robert Pawlowski Thomas Ruggeri Patrick Chiang Mattan Erez http://www.mdpi.com/2079-9268/1/2/327 A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system clock in low-power, battery-powered and energy harvesting systems. Journal of Low Power Electronics and Applications 2011-09-20 1 2 Technical Note 10.3390/jlpea1020327 327 333 2079-9268 2011-09-20 doi: 10.3390/jlpea1020327 Oleg Nizhnik Kohei Higuchi Kazusuke Maenaka http://www.mdpi.com/2079-9268/1/2/303 The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism. Journal of Low Power Electronics and Applications 2011-09-14 1 2 Article 10.3390/jlpea1020303 303 326 2079-9268 2011-09-14 doi: 10.3390/jlpea1020303 Ching-Hwa Cheng http://www.mdpi.com/2079-9268/1/2/277 Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption. Journal of Low Power Electronics and Applications 2011-07-08 1 2 Article 10.3390/jlpea1020277 277 302 2079-9268 2011-07-08 doi: 10.3390/jlpea1020277 Ramesh Vaddi Rajendra P. Agarwal Sudeb Dasgupta Tony T. Kim http://www.mdpi.com/2079-9268/1/2/261 CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing. Journal of Low Power Electronics and Applications 2011-07-04 1 2 Review 10.3390/jlpea1020261 261 276 2079-9268 2011-07-04 doi: 10.3390/jlpea1020261 Bharadwaj Amrutur Nandish Mehta Satyam Dwivedi Ajit Gupte http://www.mdpi.com/2079-9268/1/2/247 This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency. Journal of Low Power Electronics and Applications 2011-06-24 1 2 Article 10.3390/jlpea1020247 247 260 2079-9268 2011-06-24 doi: 10.3390/jlpea1020247 Suat U. Ay http://www.mdpi.com/2079-9268/1/1/219 Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation. Journal of Low Power Electronics and Applications 2011-05-19 1 1 Article 10.3390/jlpea1010219 219 246 2079-9268 2011-05-19 doi: 10.3390/jlpea1010219 Inna Vaisband Eby G. Friedman Ran Ginosar Avinoam Kolodny http://www.mdpi.com/2079-9268/1/1/204 As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV. Journal of Low Power Electronics and Applications 2011-05-16 1 1 Article 10.3390/jlpea1010204 204 218 2079-9268 2011-05-16 doi: 10.3390/jlpea1010204 Adam Teman Lidor Pergament Omer Cohen Alexander Fish http://www.mdpi.com/2079-9268/1/1/175 Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for implantable devices, with specific focus on developing efficacious but computationally efficient algorithms to detect seizures. Common seizure detection features used to construct algorithms are evaluated and algorithmic, mathematical as well as circuit-level design techniques are suggested to effectively translate the algorithms into hardware implementations on low-power platforms. Journal of Low Power Electronics and Applications 2011-05-12 1 1 Review 10.3390/jlpea1010175 175 203 2079-9268 2011-05-12 doi: 10.3390/jlpea1010175 Shriram Raghunathan Sumeet K. Gupta Himanshu S. Markandeya Pedro P. Irazoqui Kaushik Roy http://www.mdpi.com/2079-9268/1/1/150 Intelligent biomedical devices implies systems that are able to detect specific physiological processes in patients so that particular responses can be generated. This closed-loop capability can have enormous clinical value when we consider the unprecedented modalities that are beginning to emerge for sensing and stimulating patient physiology. Both delivering therapy (e.g., deep-brain stimulation, vagus nerve stimulation, etc.) and treating impairments (e.g., neural prosthesis) requires computational devices that can make clinically relevant inferences, especially using minimally-intrusive patient signals. The key to such devices is algorithms that are based on data-driven signal modeling as well as hardware structures that are specialized to these. This paper discusses the primary application-domain challenges that must be overcome and analyzes the most promising methods for this that are emerging. We then look at how these methods are being incorporated in ultra-low-energy computational platforms and systems. The case study for this is a seizure-detection SoC that includes instrumentation and computation blocks in support of a system that exploits patient-specific modeling to achieve accurate performance for chronic detection. The SoC samples each EEG channel at a rate of 600 Hz and performs processing to derive signal features on every two second epoch, consuming 9 μJ/epoch/channel. Signal feature extraction reduces the data rate by a factor of over 40×, permitting wireless communication from the patient’s head while reducing the total power on the head by 14×. Journal of Low Power Electronics and Applications 2011-04-26 1 1 Review 10.3390/jlpea1010150 150 174 2079-9268 2011-04-26 doi: 10.3390/jlpea1010150 Naveen Verma Kyong Ho Lee Ali Shoeb http://www.mdpi.com/2079-9268/1/1/131 A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current. Journal of Low Power Electronics and Applications 2011-04-15 1 1 Article 10.3390/jlpea1010131 131 149 2079-9268 2011-04-15 doi: 10.3390/jlpea1010131 Emre Salman Qi Qi http://www.mdpi.com/2079-9268/1/1/109 This paper describes the hardware requirements and design constraints that derive from unique features of body sensor networks (BSNs). Based on the BSN requirements, we examine the tradeoff between custom hardware and commercial off the shelf (COTS) designs for BSNs. The broad range of BSN applications includes situations where either custom chips or COTS design is optimal. For both types of nodes, we survey key techniques to improve energy efficiency in BSNs and identify general approaches to energy efficiency in this space. Journal of Low Power Electronics and Applications 2011-04-11 1 1 Review 10.3390/jlpea1010109 109 130 2079-9268 2011-04-11 doi: 10.3390/jlpea1010109 Yanqing Zhang Yousef Shakhsheer Adam T. Barth Harry C. Powell Jr. Samuel A. Ridenour Mark A. Hanson John Lach Benton H. Calhoun http://www.mdpi.com/2079-9268/1/1/97 Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal. Journal of Low Power Electronics and Applications 2011-04-06 1 1 Article 10.3390/jlpea1010097 97 108 2079-9268 2011-04-06 doi: 10.3390/jlpea1010097 Marco Lanuzza Fabio Frustaci Stefania Perri Pasquale Corsonello http://www.mdpi.com/2079-9268/1/1/77 In digital pixel sensors (DPS), memory elements typically occupy large silicon area of the pixel, which significantly reduces the pixel’s fill factor while increases its size, power and cost. In this work, we propose to reduce DPS memory’s area and power overhead by reducing the memory requirements with a multi-reset integration scheme, and meanwhile employing a dynamic memory instead of traditionally exploited large 6T-SRAM cell. The operation of the DPS takes advantage from the chronological change of the code, which results in reduced memory needs without affecting the light resolution. In the proposed implementation, a 4-bit in-pixel memory is used to reduce the pixel size, and an 8-bit resolution is achieved with multi-reset scheme. In addition, full complementary metal-oxide-semiconductor (CMOS) 2T DRAM and selective refresh scheme are adoptedto implement the memory elements and further increase the area savings. This paper presents the proposed multi-reset integration methodology and its implementation with dedicated memory circuits. Proposed architecture is validated by a prototype chip fabricated using AMS 0.35 μm CMOS technology. Reported experimental results are compared with relative works. Journal of Low Power Electronics and Applications 2011-03-28 1 1 Article 10.3390/jlpea1010077 77 96 2079-9268 2011-03-28 doi: 10.3390/jlpea1010077 Xiaoxiao Zhang Sylvain Leomant Ka Lai Lau Amine Bermak http://www.mdpi.com/2079-9268/1/1/59 A variety of solutions for widening the dynamic range (DR) of CMOS image sensors have been proposed throughout the years. These solutions can be categorized into different groups according to the principle used for DR widening. One of the methods, which is based on autonomous control over the integration time, was implemented by our group. We proposed the multiple resets algorithm, which was successfully implemented in three generations of WDR image sensors. While achieving the same goal of widening the DR of the sensor, each of the implemented imagers had a different architecture, and therefore presented different performance and power figures. This paper reviews designs of the aforementioned sensors and presents a comprehensive analysis of their power consumption. Power-performance tradeoffs are also discussed. Advantages and disadvantages of each sensor are presented. Journal of Low Power Electronics and Applications 2011-03-14 1 1 Review 10.3390/jlpea1010059 59 76 2079-9268 2011-03-14 doi: 10.3390/jlpea1010059 Arthur Spivak Adam Teman Alex Belenky Orly Yadid-Pecht Alexander Fish http://www.mdpi.com/2079-9268/1/1/45 In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks—one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplication operation enabling up to 80% savings in terms of silicon area and power compared to oblique based-DT while achieving 91.36% classification accuracy without throughput degradation. The circuit was designed in 0.18 μm Charter CMOS process and tested using a data set acquired with in-house fabricated tin-oxide gas sensors. Journal of Low Power Electronics and Applications 2011-03-09 1 1 Article 10.3390/jlpea1010045 45 58 2079-9268 2011-03-09 doi: 10.3390/jlpea1010045 Qingzheng Li Amine Bermak http://www.mdpi.com/2079-9268/1/1/20 Ultra low power circuits require robust and reliable operation despite the unavoidable use of low currents and the weak inversion transistor operation region. For analogue domain filtering doubly terminated LC ladder based filter topologies are thus highly desirable as they have very low sensitivities to component values: non-exact component values have a minimal effect on the realised transfer function. However, not all transfer functions are suitable for implementation via a LC ladder prototype, and even when the transfer function is suitable the synthesis procedure is not trivial. The modern circuit designer can thus benefit from an updated treatment of this synthesis procedure. This paper presents a methodology for the design of doubly terminated LC ladder structures making use of the symbolic maths engines in programs such as MATLAB and MAPLE. The methodology is explained through the detailed synthesis of an example 7th order bandpass filter transfer function for use in electroencephalogram (EEG) analysis. Journal of Low Power Electronics and Applications 2011-01-28 1 1 Review 10.3390/jlpea1010020 20 44 2079-9268 2011-01-28 doi: 10.3390/jlpea1010020 Alexander J. Casson Esther Rodriguez-Villegas http://www.mdpi.com/2079-9268/1/1/1 Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints. Journal of Low Power Electronics and Applications 2011-01-25 1 1 Review 10.3390/jlpea1010001 1 19 2079-9268 2011-01-25 doi: 10.3390/jlpea1010001 David Bol