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J. Low Power Electron. Appl. 2014, 4(3), 168-187; doi:10.3390/jlpea4030168
Review

Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

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Received: 14 March 2014; in revised form: 20 June 2014 / Accepted: 27 June 2014 / Published: 7 July 2014
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
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Abstract: Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range.
Keywords: digital CMOS circuits; ultra-low power; subthreshold logic; FDSOI; back gate biasing;variability; leakage currents; yield digital CMOS circuits; ultra-low power; subthreshold logic; FDSOI; back gate biasing; variability; leakage currents; yield
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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MDPI and ACS Style

de Streel, G.; Bol, D. Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level. J. Low Power Electron. Appl. 2014, 4, 168-187.

AMA Style

de Streel G, Bol D. Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level. Journal of Low Power Electronics and Applications. 2014; 4(3):168-187.

Chicago/Turabian Style

de Streel, Guerric; Bol, David. 2014. "Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level." J. Low Power Electron. Appl. 4, no. 3: 168-187.


J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert