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Special Issue "Special Issue on the 2017 International Image Sensor Workshop (IISW)"

A special issue of Sensors (ISSN 1424-8220).

Deadline for manuscript submissions: closed (31 October 2017)

Special Issue Editors

Guest Editor
Mr. Vladimir Koifman

Analog Value Ltd., 32 Burla St. Rishon Lezion, 75736 Israel
Website | E-Mail
Interests: CCD and CMOS image sensors; pinned photodiodes; pixel; 1/f and RTS noise; global shutter and rolling shutter sensors; high dynamic range imaging; time-of-flight imagers; X-ray imagers, astronomy and space imaging; photon counting; novel image sensor concepts
Co-Guest Editor
Prof. Dr. Shoji Kawahito

Imaging Devices Laboratory, Research Institute of Electronics, Shizuoka University, 3-5-1, Johoku, Naka-ku, Hamamatsu, 432-8011, Japan
Website | E-Mail
Co-Guest Editor
Dr. Daniel Van Blerkom

Forza Silicon Corp., 2947 Bradley Street, Suite 130, Pasadena, CA 91107, USA
Website | E-Mail
Interests: CMOS image sensors; infrared ROICs; X-ray sensors; low noise readouts; image sensor ADC architecture; stacked sensors; global shutter sensors; pixel design; pixel process/device simulation; HDR sensor design
Co-Guest Editor
Dr. Guy Meynants

ams Sensors, Coveliersstraat 15, 2600 Antwerpen, Belgium
Website | E-Mail
Interests: CMOS image sensors; global shutter pixels; high frame rate image sensors; read noise, large area imagers; high dynamic range imaging; ADCs for image sensors; miniature camera modules

Special Issue Information

Dear Colleagues,

The International Image Sensor Workshop (IISW) is the world’s largest technology forum, fully devoted to image sensor design and research. The workshop papers span across a wide range of imaging devices: From small pixel mobile image sensors to large format X-ray and astronomy imagers, from sensors for high end scientific applications to low-cost mass produced stacked sensors, from time-resolving and photon counting imagers to rad-hard sensors for space applications.

This Special Issue provides the expanded versions of 20 invited papers from the workshop covering novel and innovative approaches in image sensors, as well as state-of-the-art incremental improvements on known techniques.

Other paper submissions are strictly limited to IISW 2017 participants.

Mr. Vladimir Koifman
Prof. Dr. Shoji Kawahito
Dr. Guy Meynants
Dr. Daniel Van Blerkom
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Sensors is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CCD
  • CMOS Sensor
  • CMOS Pixel
  • Photodiode
  • 1/f Noise
  • Flicker Noise
  • RTN
  • RTS Noise
  • HDR
  • WDR
  • Dark current
  • Conversion gain
  • Photon counting
  • Single photon detection
  • BSI
  • FSI
  • Global shutter
  • Rolling shutter

Published Papers (7 papers)

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Research

Open AccessArticle An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process
Sensors 2018, 18(1), 203; doi:10.3390/s18010203
Received: 10 November 2017 / Revised: 22 December 2017 / Accepted: 7 January 2018 / Published: 12 January 2018
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Abstract
To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm
[...] Read more.
To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke. Readout noise under the highest pixel gain condition is 1 e with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias
Sensors 2018, 18(1), 118; doi:10.3390/s18010118
Received: 30 October 2017 / Revised: 28 December 2017 / Accepted: 28 December 2017 / Published: 3 January 2018
PDF Full-text (7346 KB) | HTML Full-text | XML Full-text
Abstract
A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes
[...] Read more.
A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors
Sensors 2017, 17(12), 2867; doi:10.3390/s17122867
Received: 31 October 2017 / Revised: 23 November 2017 / Accepted: 8 December 2017 / Published: 10 December 2017
PDF Full-text (5441 KB) | HTML Full-text | XML Full-text
Abstract
Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras
[...] Read more.
Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III–V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Development of Gentle Slope Light Guide Structure in a 3.4 μm Pixel Pitch Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology
Sensors 2017, 17(12), 2860; doi:10.3390/s17122860
Received: 31 October 2017 / Revised: 4 December 2017 / Accepted: 6 December 2017 / Published: 9 December 2017
PDF Full-text (7381 KB) | HTML Full-text | XML Full-text
Abstract
CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is
[...] Read more.
CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is remarkable in small pixel pitch. The newly developed 3.4 µm pitch GS CIS solves this problem by using multiple accumulation shutter technology and the gentle slope light guide structure. As a result, the developed GS pixel achieves 1.8 e temporal noise and 16,200 e full well capacity with charge domain memory in 120 fps operation. The sensitivity and parasitic light sensitivity are 28,000 e/lx·s and −89 dB, respectively. Moreover, the incident light angle dependence of sensitivity and parasitic light sensitivity are improved by the gentle slope light guide structure. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Recent Enhancements to Interline and Electron Multiplying CCD Image Sensors
Sensors 2017, 17(12), 2841; doi:10.3390/s17122841
Received: 26 September 2017 / Revised: 28 November 2017 / Accepted: 30 November 2017 / Published: 7 December 2017
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Abstract
This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced
[...] Read more.
This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced by 6 dB. By reducing the depth of the shallow photodiode (PD) implants, the photodiode-to-vertical-charge-coupled-device (VCCD) transfer gate voltage required for no-lag operation was reduced by 3 V, and the electronic shutter voltage was reduced by 9 V. The thinner, surface pinning layer also resulted in a reduction of smear by 4 dB in the blue portion of the visible spectrum. For EMCCDs, gain aging was eliminated by providing an oxide-only dielectric under its multiplication phase, while retaining the oxide-nitride-oxide (ONO) gate dielectrics elsewhere in the device. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel
Sensors 2017, 17(12), 2816; doi:10.3390/s17122816
Received: 16 October 2017 / Revised: 28 November 2017 / Accepted: 28 November 2017 / Published: 5 December 2017
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Abstract
A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of
[...] Read more.
A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e/s at 60 °C, an ultra-low read noise of 0.90 e·rms, a high full well capacity (FWC) of 4100 e, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Open AccessArticle Statistical Analysis of the Random Telegraph Noise in a 1.1 μm Pixel, 8.3 MP CMOS Image Sensor Using On-Chip Time Constant Extraction Method
Sensors 2017, 17(12), 2704; doi:10.3390/s17122704
Received: 18 October 2017 / Revised: 20 November 2017 / Accepted: 21 November 2017 / Published: 23 November 2017
PDF Full-text (13577 KB) | HTML Full-text | XML Full-text
Abstract
A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source.
[...] Read more.
A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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