A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel†
AbstractA submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e−·rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. View Full-Text
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Takahashi, S.; Huang, Y.-M.; Sze, J.-J.; Wu, T.-T.; Guo, F.-S.; Hsu, W.-C.; Tseng, T.-H.; Liao, K.; Kuo, C.-C.; Chen, T.-H.; Chiang, W.-C.; Chuang, C.-H.; Chou, K.-Y.; Chung, C.-H.; Chou, K.-Y.; Tseng, C.-H.; Wang, C.-J.; Yaung, D.-N. A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel. Sensors 2017, 17, 2816.
Takahashi S, Huang Y-M, Sze J-J, Wu T-T, Guo F-S, Hsu W-C, Tseng T-H, Liao K, Kuo C-C, Chen T-H, Chiang W-C, Chuang C-H, Chou K-Y, Chung C-H, Chou K-Y, Tseng C-H, Wang C-J, Yaung D-N. A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel. Sensors. 2017; 17(12):2816.Chicago/Turabian Style
Takahashi, Seiji; Huang, Yi-Min; Sze, Jhy-Jyi; Wu, Tung-Ting; Guo, Fu-Sheng; Hsu, Wei-Cheng; Tseng, Tung-Hsiung; Liao, King; Kuo, Chin-Chia; Chen, Tzu-Hsiang; Chiang, Wei-Chieh; Chuang, Chun-Hao; Chou, Keng-Yu; Chung, Chi-Hsien; Chou, Kuo-Yu; Tseng, Chien-Hsien; Wang, Chuan-Joung; Yaung, Dun-Nien. 2017. "A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel." Sensors 17, no. 12: 2816.
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