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Sensors 2017, 17(12), 2816; doi:10.3390/s17122816

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu 300, Taiwan
This paper is an expanded version of our published paper: Takahashi, S.; Huang, Y.-M.; Sze, J.-J.;Wu, T.-T.; Guo, F.-S.; Hsu,W.-C.; Tseng, T-H.; Liao, K.; Kuo, C.-C.; Chen, T.-H.; et al. Low Dark Current and Low Noise 0.9 m Pixel in a 45 nm Stacked CMOS Image Sensor Process Technology. In Proceedings of the 2017 International Image Sensor Workshop, Hiroshima, Japan, 30 May–2 June 2017.
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Received: 16 October 2017 / Revised: 28 November 2017 / Accepted: 28 November 2017 / Published: 5 December 2017
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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Abstract

A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e/s at 60 °C, an ultra-low read noise of 0.90 e·rms, a high full well capacity (FWC) of 4100 e, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. View Full-Text
Keywords: submicron pixel; image sensor; stacked CMOS image sensor; dark current; read noise; random telegraph noise; full well capacity; optical crosstalk submicron pixel; image sensor; stacked CMOS image sensor; dark current; read noise; random telegraph noise; full well capacity; optical crosstalk
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

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Takahashi, S.; Huang, Y.-M.; Sze, J.-J.; Wu, T.-T.; Guo, F.-S.; Hsu, W.-C.; Tseng, T.-H.; Liao, K.; Kuo, C.-C.; Chen, T.-H.; Chiang, W.-C.; Chuang, C.-H.; Chou, K.-Y.; Chung, C.-H.; Chou, K.-Y.; Tseng, C.-H.; Wang, C.-J.; Yaung, D.-N. A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel. Sensors 2017, 17, 2816.

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