E-Mail Alert

Add your e-mail address to receive forthcoming issues of this journal:

Journal Browser

Journal Browser

Special Issue "High-k Materials and Devices 2014"

Quicklinks

A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Materials for Energy Applications".

Deadline for manuscript submissions: closed (15 January 2014)

Special Issue Editor

Guest Editor
Prof. Dr. Durga Misra (Website)

Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark, NJ 07102 USA
Interests: High-K Dielectrics Materials and Devices; Gate Stack Reliability; CMOS Devices on Alternate Substrates; Photodiodes

Special Issue Information

Dear Colleagues,

Advanced gate stacks with high dielectric constant materials (high-k) for complementary metal-oxide-semiconductor (CMOS) and memory applications in sub-22 nm feature size integrated circuits have been a subject of intense research in recent years. The main focus of the forthcoming special issue is to present a comprehensive overview to our readers by assembling state-of-the-art research articles and reviews on processing and characterization of high-k gate material. The topics covered by this special issue include high-k materials and deposition methods; Deposition on high-mobility substrate such as Ge, GaAs, and other III-V compounds; Interface passivation of substrate/high-k interface; Reliability of high-k material; Characterization techniques and Application to non-volatile memory systems.

Prof. Dr. Durga Misra
Guest Editor

Submission

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. Papers will be published continuously (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are refereed through a peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Materials is an international peer-reviewed Open Access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs).

Published Papers (7 papers)

View options order results:
result details:
Displaying articles 1-7
Export citation of selected articles as:

Research

Jump to: Review

Open AccessArticle Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement
Materials 2014, 7(10), 6965-6981; doi:10.3390/ma7106965
Received: 15 January 2014 / Revised: 29 September 2014 / Accepted: 8 October 2014 / Published: 13 October 2014
Cited by 5 | PDF Full-text (808 KB) | HTML Full-text | XML Full-text
Abstract
Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse [...] Read more.
Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Figures

Open AccessArticle Characterization of High-k Nanolayers by Grazing Incidence X-ray Spectrometry
Materials 2014, 7(4), 3147-3159; doi:10.3390/ma7043147
Received: 21 January 2014 / Revised: 27 March 2014 / Accepted: 8 April 2014 / Published: 17 April 2014
Cited by 9 | PDF Full-text (697 KB) | HTML Full-text | XML Full-text
Abstract
The accurate characterization of nanolayered systems is an essential topic for today’s developments in many fields of material research. Thin high-k layers and gate stacks are technologically required for the design of current and future electronic devices and can be deposited, e.g., [...] Read more.
The accurate characterization of nanolayered systems is an essential topic for today’s developments in many fields of material research. Thin high-k layers and gate stacks are technologically required for the design of current and future electronic devices and can be deposited, e.g., by Atomic Layer Deposition (ALD). However, the metrological challenges to characterize such systems demand further development of analytical techniques. Reference-free Grazing Incidence X-ray Fluorescence (GIXRF) based on synchrotron radiation can significantly contribute to the characterization of such nanolayered systems. GIXRF takes advantage of the incident angle dependence of XRF, in particular below the substrate’s critical angle where changes in the X-ray Standing Wave field (XSW) intensity influence the angular intensity profile. The reliable modeling of the XSW in conjunction with the radiometrically calibrated instrumentation at the PTB allows for reference-free, fundamental parameter-based quantitative analysis. This approach is very well suited for the characterization of nanoscaled materials, especially when no reference samples with sufficient quality are available. The capabilities of this method are demonstrated by means of two systems for transistor gate stacks, i.e., Al2O3 high-k layers grown on Si or Si/SiO2 and Sc2O3 layers on InGaAs/InP substrates. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Figures

Review

Jump to: Research

Open AccessReview Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm
Materials 2014, 7(7), 5117-5145; doi:10.3390/ma7075117
Received: 15 January 2014 / Revised: 2 July 2014 / Accepted: 3 July 2014 / Published: 15 July 2014
Cited by 16 | PDF Full-text (2011 KB) | HTML Full-text | XML Full-text
Abstract
Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and [...] Read more.
Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Open AccessReview Emerging Applications for High K Materials in VLSI Technology
Materials 2014, 7(4), 2913-2944; doi:10.3390/ma7042913
Received: 27 January 2014 / Revised: 14 March 2014 / Accepted: 24 March 2014 / Published: 10 April 2014
Cited by 11 | PDF Full-text (1040 KB) | HTML Full-text | XML Full-text
Abstract
The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. [...] Read more.
The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Figures

Open AccessReview Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices
Materials 2014, 7(4), 2669-2696; doi:10.3390/ma7042669
Received: 13 January 2014 / Revised: 19 March 2014 / Accepted: 25 March 2014 / Published: 31 March 2014
Cited by 3 | PDF Full-text (1645 KB) | HTML Full-text | XML Full-text
Abstract
A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) [...] Read more.
A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Figures

Open AccessReview Germanium Based Field-Effect Transistors: Challenges and Opportunities
Materials 2014, 7(3), 2301-2339; doi:10.3390/ma7032301
Received: 18 January 2014 / Revised: 6 March 2014 / Accepted: 7 March 2014 / Published: 19 March 2014
Cited by 19 | PDF Full-text (1482 KB) | HTML Full-text | XML Full-text
Abstract
The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power [...] Read more.
The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Open AccessReview A Review on Resistive Switching in High-k Dielectrics: A Nanoscale Point of View Using Conductive Atomic Force Microscope
Materials 2014, 7(3), 2155-2182; doi:10.3390/ma7032155
Received: 18 January 2014 / Revised: 13 February 2014 / Accepted: 14 February 2014 / Published: 13 March 2014
Cited by 35 | PDF Full-text (1957 KB) | HTML Full-text | XML Full-text
Abstract
Metal-Insulator-Metal (MIM) structures have raised as the most promising configuration for next generation information storage, leading to great performance and fabrication-friendly Resistive Random Access Memories (RRAM). In these cells, the memory concept is no more based on the charge storage, but on [...] Read more.
Metal-Insulator-Metal (MIM) structures have raised as the most promising configuration for next generation information storage, leading to great performance and fabrication-friendly Resistive Random Access Memories (RRAM). In these cells, the memory concept is no more based on the charge storage, but on tuning the electrical resistance of the insulating layer by applying electrical stresses to reach a high resistive state (HRS or “0”) and a low resistive state (LRS or “1”), which makes the memory point. Some high-k dielectrics show this unusual property and in the last years high-k based RRAM have been extensively analyzed, especially at the device level. However, as resistance switching (in the most promising cells) is a local phenomenon that takes place in areas of ~100 nm2, the use of characterization tools with high lateral spatial resolution is necessary. In this paper the status of resistive switching in high-k materials is reviewed from a nanoscale point of view by means of conductive atomic force microscope analyses. Full article
(This article belongs to the Special Issue High-k Materials and Devices 2014)
Figures

Journal Contact

MDPI AG
Materials Editorial Office
St. Alban-Anlage 66, 4052 Basel, Switzerland
materials@mdpi.com
Tel. +41 61 683 77 34
Fax: +41 61 302 89 18
Editorial Board
Contact Details Submit to Materials
Back to Top