Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm
Abstract
:1. Introduction
NOR flash | 2009 | 2010 | 2011 | 2012 | 2013 | 2014 |
---|---|---|---|---|---|---|
NOR flash technology node—F (nm) [21] | 50 | 45 | 40 | 35 | 32 | 28 |
A. floating gate NOR flash | ||||||
Cell size-area factor in a multiples of F2 [22,23,24,25] | 9–11 | 9–11 | 9–11 | 9–11 | 9–11 | 9–11 |
Gate length Lg, physical (nm) [26] | 110 | 110 | 100 | 100 | 90 | 90 |
Tunnel oxide thickness (nm) [27] | 8–9 | 8–9 | 8–9 | 8–9 | 8 | 8 |
Interpoly dielectric material [28] | ONO | ONO | ONO | ONO | High-k | High-k |
Interpoly dielectric thickness EOT (nm) | 13–15 | 13–15 | 13–15 | 13–15 | 8–10 | 8–10 |
Gate coupling ratio [29] | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 |
Highest W/E voltage (V) [30] | 7–9 | 7–9 | 7–9 | 7–9 | 6–8 | 6–8 |
Iread (μA) [31] | 21–27 | 20–26 | 19–25 | 17–22 | 15–20 | 14–19 |
Endurance (erase/write cycles) [32] | 1.0 × 105 | 1.0 × 105 | 1.0 × 105 | 1.0 × 105 | 1.0 × 106 | 1.0 × 106 |
Nonvolatile date retention (years) [33] | 10–20 | 10–20 | 10–20 | 10–20 | 20 | 20 |
Maximum number of bits per cell (MLC) [34] | 2 | 2 | 2 | 2 | 2 | 2 |
Array architecture (with cell contact (CC) or virtual ground (VG)) [35] | CC | CC | CC | CC | CC/VG | CC/VG |
Year of production | 2009 | 2010 | 2011 | 2012 | 2013 | 2014 |
---|---|---|---|---|---|---|
DRAM 1/2 pitch (nm) (contacted) | 50 | 45 | 40 | 35 | 32 | 28 |
MPU/ASIC metal I (MI) 1/2 PITCH (nm) contacted | 54 | 45 | 38 | 32 | 27 | 24 |
(ORTC) NAND flash poly 1/2 pitch (nm) | 38 | 32 | 28 | 25 | 23 | 20 |
(PIDS) NAND flash poly 1/2 pitch (nm) | 34 | 32 | 28 | 25 | 22 | 20 |
NAND flash | ||||||
NAND flash technology node—F (nm) [1] | 34 | 32 | 28 | 25 | 22 | 20 |
Number of word lines in one NAND string [2] | 64 | 64 | 64 | 64 | 64 | 64 |
Cell type (FG, CT, 3D, etc.) [3] | FG | FG | FG | FG/CT | FG/CT | CT/3D |
3D NAND number of memory layers | 1 | 1 | 1 | 1 | 1 | 2 |
A. Floating gate NAND flash | ||||||
Cell size-area factor in a multiples of F2 SLC/MLC [4] | 4.0/1.3 | 4.0/1.3 | 4.0/1.3 | 4.0/1.0 | 4.0/1.0 | 4.0/1.0 |
Tunnel oxide thickness (nm) [5] | 6–7 | 6–7 | 6–7 | 6–7 | 6–7 | 6–7 |
Interpoly dielectric material [6] | ONO | ONO | ONO | High-k | High-k | High-k |
Interpoly dielectric thickness (nm) | 10–13 | 10–13 | 10–13 | 9–10 | 9–10 | 9–10 |
Gate coupling ratio (GCR) [7] | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 | 0.6–0.7 |
Control gate material [8] | n-Poly | n-Poly | n-Poly | Poly/metal | Poly/metal | Poly/metal |
Highest W/E voltage (V) [9] | 17–19 | 17–19 | 17–19 | 15–17 | 15–17 | 15–17 |
Endurance (erase/write cycles) [10] | 1.0 × 105 | 1.0 × 105 | 1.0 × 105 | 1.0 × 104 | 1.0 × 104 | 1.0 × 104 |
Nonvolatile date retention (years) [11] | 10–20 | 10–20 | 10–20 | 10–20 | 10–20 | 20 |
Maximum number of bits per cell (MLC) [12] | 3 | 3 | 3 | 4 | 4 | 4 |
2. Background Knowledge
3. Recent Developments
3.1. Charge Trapping Layer
High-k as CT Layer | Deposition Technique | Program/Erase Characteristic | Endurance Characteristics | Retention Characteristics | |
---|---|---|---|---|---|
Si3N4 + HfON | The layers of the TaN-[SiO2-LaAlO3]-[Si3N4-HfON]-[LaAlO3-SiO2]-Si devices comprised 2.5 nm of thermal SiO2, 2.5 nm of PVD LaAlO3, 5 nm of reactive PVD HfON0.2 and 5 nm of Si3N4 by LPCVD. Then 8 nm LaAlO3 by PVD, 5 nm SiO2 by PECVD, and 200 nm TaN by PVD. This was followed by standard gate definition, self-aligned P+ implantation and an RTA. | 150 °C and ± 16 V program/erase (P/E), the device showed P/E speed of 100 μs, an initial ΔVth window of 5.6 V. | a large 105-cycle window of 4.9 V and 103-cycled 10-year retention window of 4.1 V, at ±16 V 100 μs P/E. | An initial ΔVth window of 5.6 V is set and later extrapolated 10 year retention of 3.8 V. | |
ZrON | ZrON film was deposited in a reactive magnetron sputtering system as the charge-trapping layer. To form the ZrON film, a pure Zr target was sputtered in an oxygen (4-sccm)/nitrogen (12-sccm)/argon mixture (24-sccm) gas ambient. A subsequent annealing was performed on some as-deposited samples in a N2 ambient at 600 °C for 30 min. | 3.81 V hysteresis memory window by ±7 V P/E voltage and 1.98 V flat-band voltage shift by programming at +7 V for 10 ms. | negligible degradation of the memory window up to 105 P/E cycles from the endurance measurement, in which ±7 V with 10 ms gate pulse-width used. | 28.6% charge loss after ten-year operation at 85 °C. | |
HfO2 | After a growth of thermal oxide with a thickness of 3 nm at 700 °C in dry O2 ambient, a deposition of HfO2 layers ranging from 8 to 2 nm was followed by atomic layered chemical vapor deposition method at 300 °C to evaluate the effect of thickness on the charge trapping and tunneling characteristics. | The memory window for 8 nm HfO2 layer is 1.5 V at high frequency of 1 MHz and sweep voltage of ±5 V. | insufficient data given. | An initial memory window of 6.16 V; after 10 years, the memory window of 4.26 V. Charge loss rate of 30.8%. | |
Hf1−x−yNxOy | A 9-nm Hf1−x−yNxOy layer was deposited by reactive sputtering under a mixed O2 and N2 conditions with different O2/N2 ratios to study the N% dependence of the MONOS device integrity. | The Hf0.3N0.2O0.5 MONOS device showed ±9 V P/E voltage, 100 μs P/E speed, large initial 2.8 V memory window. | memory windows of 2.4 V and 1.7 V after 105 cycles at ±9 V 100 μs P/E for Hf0.3N0.2O0.5 devices and Hf0.35N0.10O0.55 MONOS devices, respectively. | a ten-year expected retention of 1.8 V at 85 °C or 1.5 V at 125 °C. | |
HfAlO2 | For the SOHOS device, pure HfO2 and Al2O3 films were deposited by the ALD, while HfAlO films were deposited by metal organic chemical vapor deposition using a single cocktail source. The Al2O3 concentration in HfAlO was kept at 10%. | From the programming (Vg − Vfb = 6 V) and erasing (Vg − Vfb = −6 V), memory window is 3 V at 100 ms of P/E process. | HfAlO devices show a negligible degradation in the threshold voltage window after 104 W/E cycles. | The initial Vfb after programming is 3.5 V for 12.5 nm HfAlO and after 104 s the value retains at 3.4 V. | |
Y2O3 | A 3 nm Y2O3 film was deposited on the tunneling oxide by sputtering with yttrium target in a system with a base pressure of 9.8 × 10−3 m·bar at room temperature. The sputtering process was performed in diluted O2(Ar/O2 = 25/5) ambient sputtering power of 100 W, at sputter rates of about 2.5 Å/min. Rapid thermal process anneal of 700 °C in N2,O2, or N2O ambient for 30 s was then performed to transform Y2O3 film into Y-silicate charge trapping layer. | For the condition of VD = 6 V and VG = 8 V at 1ms, a high-k Y2O3 SONOS-type memory after N2 annealing exhibits a larger memory window of 2.43 V compared with other annealing gases. | The values of Vth in the program and erase states for Y-silicate charge trapping layer memory prepared at a N2 gas annealing did not increase significantly up to 105 P/E cycles. | An yttrium silicate trapping storage layer memory annealed in N2 gas exhibits a small charge loss of about 4% measured time up to 104 s and at 25 °C. At the temperature at 125 °C, SONOS-type memory prepared under an Y2O3 trapping layer and annealed in N2 gas has a lower charge loss of 22% during the program state compared with other annealing gases. | |
Tb2O3 | The 8 nm Tb2O3 film was deposited on the tunneling oxide by reactive sputtering in diluted O2 from a terbium target as a charge trapping layer. The wafers were annealed in O2 gas for 30 s at 800 °C by rapid thermal annealing. | Threshold voltage shifting (memory window of 1.41 V operated at Vg = 8 V at 0.1 s). | The values of VFB in the program and erase states did not increase significantly up to 105 P/E cycles. | Charge loss 10% measured time up to 104 s at 85 °C. | |
Ta2O5 | After standard clean, the substrate was first annealed in NH3 at 700 °C, 10s to improve interface quality, followed by CVD HfO2 tunneling oxide layer formation using Hafnium t-butoxide (Hf(OC4H9)4 at 500 °C. The Ta2O5 charge-trapping layer was formed by oxidation of physical vapor deposition (PVD) Ta at 550 °C. | Memory windows of about 0.8V when the device is programmed with ±8 V-1-ms gate pulse; The device can be written starting from 10 us and erased from 1 ms for 6 and 7 V. | Memory window has no obvious shrink after 10 write/erase cycles with 8 V 1 ms stress at room temperature. | Retention characteristics at room temperature and 85 °C demonstrate a decay rate of 50 mV/dec. Memory window extrapolated at ten years is 0.64 V (initial 0.8 V) at room temperature, and 0.42 V at 85 °C. | |
MoOx | The embedded MoOx layer was sputtered from the Mo target in Ar/O2(1:1) at 5 mTorr and 100 W for 15 s. The as-deposited MoOx layer was transformed into nanocrystalline MoO3, after the PDA step at 800 °C for 1 min in the pure N2 ambient by rapid thermal annealing. | The nc-MoOx sample shows a large VFB shift of −0.52 V after the −8 V stress, which corresponds to the hole trapping density of 1.14 × 1012 cm−2. On the other hand, for the same sample, a very small positive VFB shift, i.e., 0.04 V is observed after the +8 V stress. | insufficient data given. | About 54% of trapped holes (under the −8 V stress condition) remain in the sample after 10 years. Also, about 52% of trapped holes (under the −7 V stress condition) remain in the sample after 10 years. | |
SrTiO3 | 3 nm SrTiO3 was deposited on the SiO2 by reactive sputtering using a SrTiO3 target in a mixed Ar/N2 (4/1) or Ar/O2 (4/1) ambient. | memory window (8.4 V at ±10 V sweeping voltage), P/E speeds (1.8 V at 1 ms +8 V). | memory window after 105 cycles is 2.13 V compared with initial value of 2.07 V. | charge loss of 38% after 104 s. | |
BaTiO3 | 10 nm Zr-doped BaTiO3 was deposited on the SiO2 by reactive sputtering using BaTiO3 and Zr targets in a mixed Ar/O2 ambient, and the atomic ratio of Zr and Ti was determined to be 1/3. The sample went through PDA in a N2 ambient at 900 °C for 30 s. | memory window (8.3 V at ±12 V for 1 s), but higher program speed at low gate voltage (3.2 V at 100 μs +6 V). | Under a ±12 V 100 μs stress pulse the P/E windows of the Zr-BTO sample before and after the 105-cycle stressing are 6.4 and 6.6 V, respectively, and negligible degradation happens. | charge loss of 6.4% at 150 °C for 104 s. | |
Al2O3 + La2O3 + Al2O3 | Al2O3/La2O3/Al2O3 films were deposited on (100) ntype Si wafers (SILTRON, Korea) by a MOCVD system. N2 was used as a carrier gas for La and Al precursor. | maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in the program mode and at −13 V for 100 ms in the erase mode. | memory window after 104 cycles is 1.2 V compared with initial value of 1.12 V. | insufficient data given. | |
Si3N4 + Al2O3 + HfO2 | Si3N4 was deposited by low-pressure chemical vapor deposition, and Al2O3 and HfO2 were deposited using the metal–organic chemical vapor deposition method. High-temperature annealing was performed on all samples in a N2 ambient for 30 s at 900 °C by rapid thermal anneal. | at VP = 16 V and VE = −16 V for 1 s, memory window of this film of about 10 V, P/E speeds (6.1 V at 1 ms +8 V). | no sufficient data given. | charge loss of 4% after 104 s. |
3.2. Blocking Layer
3.3. Tunneling Layer
Channel Hot Electron (CHE) | Fowler-Nordheim (F-N) | |
---|---|---|
Advantages | The physical mechanism of CHE is relatively simple to understand qualitatively. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations.
At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100 kV/cm. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. A lateral electric field (between source and drain) “heats” the electrons and a transversal electric field (between channel and control gate) injects the carriers through the oxide. The programming speed of CHE for conventional floating gate memory is faster. | The F-N mechanism is widely used in NVM, particularly in EEPROM. With a relatively thick oxide (20–30 nm) one must apply a high voltage (20–30 V) to have an appreciable tunnel current. With thin oxides, the same current can be obtained by applying a much lower voltage. An optimum thickness is chosen in present devices, which use the tunneling phenomenon to tradeoff between performance constraints (programming speed, power consumption, etc.) and reliability concerns. There are three main reasons for this choice:
|
Disadvantages | The probability of the injecting electrons is quite low and hot electron injection is an inefficient method of programming. For an electron to overcome the potential barrier, three requirements must be meet accordingly:
| The exponential dependence of tunnel current on the oxide-electric field causes some critical problems of process control because. Very small variation of oxide thickness among the cells in a memory array produces a great difference in programming or erasing currents.
Bad quality oxides are rich of interface and bulk traps, and trap-assisted tunneling is made possible since the equivalent barrier height seen by electrons is reduced and tunneling requires a much lower oxide field than 10 MV/cm. The oxide defects must be avoided to control program/erase characteristics and to have good reliability. Frequent program and erase operations induce an increase of trapped charge in the oxide. This affects the barrier height, which is lower in the case of positive and higher in the case of negative trapping, respectively, thus increasing or decreasing the tunnel currents. |
4. Conclusions
Acknowledgments
Author Contributions
Conflicts of Interest
References
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Zhao, C.; Zhao, C.Z.; Taylor, S.; Chalker, P.R. Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm. Materials 2014, 7, 5117-5145. https://doi.org/10.3390/ma7075117
Zhao C, Zhao CZ, Taylor S, Chalker PR. Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm. Materials. 2014; 7(7):5117-5145. https://doi.org/10.3390/ma7075117
Chicago/Turabian StyleZhao, Chun, Ce Zhou Zhao, Stephen Taylor, and Paul R. Chalker. 2014. "Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm" Materials 7, no. 7: 5117-5145. https://doi.org/10.3390/ma7075117