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Special Issue "High-k Materials and Devices"

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A special issue of Materials (ISSN 1996-1944).

Deadline for manuscript submissions: closed (31 December 2011)

Special Issue Editor

Guest Editor
Dr. Koji Kita (Website)

Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan
Fax: +81 3 5841 7161
Interests: dielectric materials; high-k; germanium FETs; interface properties

Published Papers (10 papers)

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Research

Jump to: Review

Open AccessArticle Electrical Characteristics of the Uniaxial-Strained nMOSFET with a Fluorinated HfO2/SiON Gate Stack
Materials 2014, 7(3), 2370-2381; doi:10.3390/ma7032370
Received: 3 January 2014 / Revised: 10 March 2014 / Accepted: 12 March 2014 / Published: 20 March 2014
Cited by 1 | PDF Full-text (398 KB) | HTML Full-text | XML Full-text
Abstract
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO2/SiON) gate stack. The SiN CESL process clearly improves [...] Read more.
The channel fluorine implantation (CFI) process was integrated with the Si3N4 contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO2/SiON) gate stack. The SiN CESL process clearly improves basic electrical performance, due to induced uniaxial tensile strain within the channel. However, further integrating of the CFI process with the SiN CESL-strained nMOSFET exhibits nearly identical transconductance, subthreshold swing, drain current, gate leakage and breakdown voltage, which indicates that the strain effect is not affected by the fluorine incorporation. Moreover, hydrogen will diffuse toward the interface during the SiN deposition, then passivate dangling bonds to form weak Si-H bonds, which is detrimental for channel hot electron stress (CHES). Before hydrogen diffusion, fluorine can be used to terminate oxygen vacancies and dangling bonds, which can create stronger Hf-F and Si-F bonds to resist consequent stress. Accordingly, the reliability of constant voltage stress (CVS) and CHES for the SiN CESL uniaxial-strained nMOSFET can be further improved by the fluorinated HfO2/SiON using the CFI process. Nevertheless, the nMOSFET with either the SiN CESL or CFI process exhibits less charge detrapping, which means that a greater part of stress-induced charges would remain in the gate stack after nitrogen (SiN CESL) or fluorine (CFI) incorporation. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessArticle Electrical Properties of Thin-Film Capacitors Fabricated Using High Temperature Sputtered Modified Barium Titanate
Materials 2012, 5(4), 644-660; doi:10.3390/ma5040644
Received: 5 January 2012 / Revised: 27 March 2012 / Accepted: 29 March 2012 / Published: 13 April 2012
Cited by 5 | PDF Full-text (626 KB) | HTML Full-text | XML Full-text
Abstract
Simple thin-film capacitor stacks were fabricated from sputter-deposited doped barium titanate dielectric films with sputtered Pt and/or Ni electrodes and characterized electrically. Here, we report small signal, low frequency capacitance and parallel resistance data measured as a function of applied DC bias, [...] Read more.
Simple thin-film capacitor stacks were fabricated from sputter-deposited doped barium titanate dielectric films with sputtered Pt and/or Ni electrodes and characterized electrically. Here, we report small signal, low frequency capacitance and parallel resistance data measured as a function of applied DC bias, polarization versus applied electric field strength and DC load/unload experiments. These capacitors exhibited significant leakage (in the range 8–210 μA/cm2) and dielectric loss. Measured breakdown strength for the sputtered doped barium titanate films was in the range 200 kV/cm −2 MV/cm. For all devices tested, we observed clear evidence for dielectric saturation at applied electric field strengths above 100 kV/cm: saturated polarization was in the range 8–15 μC/cm2. When cycled under DC conditions, the maximum energy density measured for any of the capacitors tested here was ~4.7 × 10−2 W-h/liter based on the volume of the dielectric material only. This corresponds to a specific energy of ~8 × 10−3 W-h/kg, again calculated on a dielectric-only basis. These results are compared to those reported by other authors and a simple theoretical treatment provided that quantifies the maximum energy that can be stored in these and similar devices as a function of dielectric strength and saturation polarization. Finally, a predictive model is developed to provide guidance on how to tailor the relative permittivities of high-k dielectrics in order to optimize their energy storage capacities. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessArticle Sputtered Modified Barium Titanate for Thin-Film Capacitor Applications
Materials 2012, 5(4), 575-589; doi:10.3390/ma5040575
Received: 3 March 2012 / Revised: 26 March 2012 / Accepted: 28 March 2012 / Published: 10 April 2012
Cited by 10 | PDF Full-text (2004 KB) | HTML Full-text | XML Full-text
Abstract
New apparatus and a new process for the sputter deposition of modified barium titanate thin-films were developed. Films were deposited at temperatures up to 900 °C from a Ba0.96Ca0.04Ti0.82Zr0.18O3 [...] Read more.
New apparatus and a new process for the sputter deposition of modified barium titanate thin-films were developed. Films were deposited at temperatures up to 900 °C from a Ba0.96Ca0.04Ti0.82Zr0.18O3 (BCZTO) target directly onto Si, Ni and Pt surfaces and characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). Film texture and crystallinity were found to depend on both deposition temperature and substrate: above 600 °C, the as-deposited films consisted of well-facetted crystallites with the cubic perovskite structure. A strongly textured Pt (111) underlayer enhanced the (001) orientation of BCZTO films deposited at 900 °C, 10 mtorr pressure and 10% oxygen in argon. Similar films deposited onto a Pt (111) textured film at 700 °C and directly onto (100) Si wafers showed relatively larger (011) and diminished intensity (00ℓ) diffraction peaks. Sputter ambients containing oxygen caused the Ni underlayers to oxidize even at 700 °C: Raising the process temperature produced more diffraction peaks of NiO with increased intensities. Thin-film capacitors were fabricated using ~500 nm thick BCZTO dielectrics and both Pt and Ni top and bottom electrodes. Small signal capacitance measurements were carried out to determine capacitance and parallel resistance at low frequencies and from these data, the relative permittivity (er) and resistivity (r) of the dielectric films were calculated; values ranged from ~50 to >2,000, and from ~104 to ~1010 Ω∙cm, respectively. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessArticle Initial Processes of Atomic Layer Deposition of Al2O3 on InGaAs: Interface Formation Mechanisms and Impact on Metal-Insulator-Semiconductor Device Performance
Materials 2012, 5(3), 404-414; doi:10.3390/ma5030404
Received: 7 December 2011 / Revised: 18 January 2012 / Accepted: 4 March 2012 / Published: 8 March 2012
Cited by 12 | PDF Full-text (1020 KB) | HTML Full-text | XML Full-text
Abstract
Interface-formation processes in atomic layer deposition (ALD) of Al2O3 on InGaAs surfaces were investigated using on-line Auger electron spectroscopy. Al2O3 ALD was carried out by repeating a cycle of Al(CH3)3 (trimethylaluminum, TMA) adsorption [...] Read more.
Interface-formation processes in atomic layer deposition (ALD) of Al2O3 on InGaAs surfaces were investigated using on-line Auger electron spectroscopy. Al2O3 ALD was carried out by repeating a cycle of Al(CH3)3 (trimethylaluminum, TMA) adsorption and oxidation by H2O. The first two ALD cycles increased the Al KLL signal, whereas they did not increase the O KLL signal. Al2O3 bulk-film growth started from the third cycle. These observations indicated that the Al2O3/InGaAs interface was formed by reduction of the surface oxides with TMA. In order to investigate the effect of surface-oxide reduction on metal-insulator-semiconductor (MIS) properties, capacitors and field-effect transistors (FETs) were fabricated by changing the TMA dosage during the interface formation stage. The frequency dispersion of the capacitance-voltage characteristics was reduced by employing a high TMA dosage. The high TMA dosage, however, induced fixed negative charges at the MIS interface and degraded channel mobility. Full article
(This article belongs to the Special Issue High-k Materials and Devices)

Review

Jump to: Research

Open AccessReview Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices
Materials 2012, 5(8), 1413-1438; doi:10.3390/ma5081413
Received: 2 June 2012 / Revised: 24 July 2012 / Accepted: 26 July 2012 / Published: 17 August 2012
Cited by 30 | PDF Full-text (2103 KB) | HTML Full-text | XML Full-text
Abstract
High permittivity (k) gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties [...] Read more.
High permittivity (k) gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO2 and La2O3. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La2O3), are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessReview Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices
Materials 2012, 5(7), 1297-1335; doi:10.3390/ma5071297
Received: 12 May 2012 / Revised: 10 July 2012 / Accepted: 16 July 2012 / Published: 24 July 2012
Cited by 33 | PDF Full-text (856 KB) | HTML Full-text | XML Full-text
Abstract
The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN [...] Read more.
The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessReview Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements
Materials 2012, 5(6), 1005-1032; doi:10.3390/ma5061005
Received: 28 December 2011 / Revised: 24 April 2012 / Accepted: 11 May 2012 / Published: 1 June 2012
Cited by 16 | PDF Full-text (717 KB) | HTML Full-text | XML Full-text
Abstract
In capacitance-voltage (C-V) measurements, frequency dispersion in high-k dielectrics is often observed. The frequency dependence of the dielectric constant (k-value), that is the intrinsic frequency dispersion, could not be assessed before suppressing the effects of extrinsic frequency dispersion, such [...] Read more.
In capacitance-voltage (C-V) measurements, frequency dispersion in high-k dielectrics is often observed. The frequency dependence of the dielectric constant (k-value), that is the intrinsic frequency dispersion, could not be assessed before suppressing the effects of extrinsic frequency dispersion, such as the effects of the lossy interfacial layer (between the high-k thin film and silicon substrate) and the parasitic effects. The effect of the lossy interfacial layer on frequency dispersion was investigated and modeled based on a dual frequency technique. The significance of parasitic effects (including series resistance and the back metal contact of the metal-oxide-semiconductor (MOS) capacitor) on frequency dispersion was also studied. The effect of surface roughness on frequency dispersion is also discussed. After taking extrinsic frequency dispersion into account, the relaxation behavior can be modeled using the Curie-von Schweidler (CS) law, the Kohlrausch-Williams-Watts (KWW) relationship and the Havriliak-Negami (HN) relationship. Dielectric relaxation mechanisms are also discussed. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessReview Study of Direct-Contact HfO2/Si Interfaces
Materials 2012, 5(3), 512-527; doi:10.3390/ma5030512
Received: 27 February 2012 / Revised: 5 March 2012 / Accepted: 8 March 2012 / Published: 19 March 2012
Cited by 15 | PDF Full-text (881 KB) | HTML Full-text | XML Full-text
Abstract
Controlling monolayer Si oxide at the HfO2/Si interface is a challenging issue in scaling the equivalent oxide thickness of HfO2/Si gate stack structures. A concept that the author proposes to control the Si oxide interface by using ultra-high [...] Read more.
Controlling monolayer Si oxide at the HfO2/Si interface is a challenging issue in scaling the equivalent oxide thickness of HfO2/Si gate stack structures. A concept that the author proposes to control the Si oxide interface by using ultra-high vacuum electron-beam HfO2 deposition is described in this review paper, which enables the so-called direct-contact HfO2/Si structures to be prepared. The electrical characteristics of the HfO2/Si metal-oxide-semiconductor capacitors are reviewed, which suggest a sufficiently low interface state density for the operation of metal-oxide-semiconductor field-effect-transistors (MOSFETs) but reveal the formation of an unexpected strong interface dipole. Kelvin probe measurements of the HfO2/Si structures provide obvious evidence for the formation of dipoles at the HfO2/Si interfaces. The author proposes that one-monolayer Si-O bonds at the HfO2/Si interface naturally lead to a large potential difference, mainly due to the large dielectric constant of the HfO2. Dipole scattering is demonstrated to not be a major concern in the channel mobility of MOSFETs. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessReview Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices
Materials 2012, 5(3), 443-477; doi:10.3390/ma5030443
Received: 7 January 2012 / Revised: 8 February 2012 / Accepted: 6 March 2012 / Published: 14 March 2012
Cited by 13 | PDF Full-text (1413 KB) | HTML Full-text | XML Full-text
Abstract
A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability [...] Read more.
A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
Open AccessReview Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?
Materials 2012, 5(3), 478-500; doi:10.3390/ma5030478
Received: 29 January 2012 / Revised: 11 February 2012 / Accepted: 6 March 2012 / Published: 14 March 2012
Cited by 49 | PDF Full-text (597 KB) | HTML Full-text | XML Full-text
Abstract
Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ ( > 20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL) is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices. Full article
(This article belongs to the Special Issue High-k Materials and Devices)
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