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Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?
AbstractCurrent status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ ( > 20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL) is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.
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Ando, T. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? Materials 2012, 5, 478-500.View more citation formats
Ando T. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? Materials. 2012; 5(3):478-500.Chicago/Turabian Style
Ando, Takashi. 2012. "Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?" Materials 5, no. 3: 478-500.
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