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J. Low Power Electron. Appl. 2013, 3(2), 159-173; doi:10.3390/jlpea3020159

A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers

1,* , 2
1 The Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA 2 Intel Corporation, Hillsboro, OR 97124, USA
* Author to whom correspondence should be addressed.
Received: 13 February 2013 / Revised: 8 April 2013 / Accepted: 25 April 2013 / Published: 24 May 2013
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
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Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking. The circuit enables flexible tuning of the offset voltage. Measurements taken from a 45 nm test chip show the circuit is able to limit the offset to 20 mV. A 16kB SRAM is designed using the auto-zeroing circuit for the sense amps. The reduction in the total read energy and delay is reported for various configurations of the memory.
Keywords: offset compensation; SRAM; sense amplifier; auto-zeroing offset compensation; SRAM; sense amplifier; auto-zeroing
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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Beshay, P.; Ryan, J.F.; Calhoun, B.H. A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers. J. Low Power Electron. Appl. 2013, 3, 159-173.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert