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J. Low Power Electron. Appl., Volume 1, Issue 2 (September 2011), Pages 247-333

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Research

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Open AccessArticle Energy Efficient Supply Boosted Comparator Design
J. Low Power Electron. Appl. 2011, 1(2), 247-260; doi:10.3390/jlpea1020247
Received: 6 April 2011 / Revised: 13 June 2011 / Accepted: 20 June 2011 / Published: 24 June 2011
Cited by 3 | PDF Full-text (1694 KB) | HTML Full-text | XML Full-text
Abstract
This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow [...] Read more.
This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Open AccessArticle Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design
J. Low Power Electron. Appl. 2011, 1(2), 277-302; doi:10.3390/jlpea1020277
Received: 16 May 2011 / Revised: 29 June 2011 / Accepted: 30 June 2011 / Published: 8 July 2011
Cited by 6 | PDF Full-text (840 KB) | HTML Full-text | XML Full-text
Abstract
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored [...] Read more.
Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Open AccessArticle Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design
J. Low Power Electron. Appl. 2011, 1(2), 303-326; doi:10.3390/jlpea1020303
Received: 16 May 2011 / Revised: 22 August 2011 / Accepted: 5 September 2011 / Published: 14 September 2011
PDF Full-text (2854 KB) | HTML Full-text | XML Full-text
Abstract
The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance [...] Read more.
The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)

Review

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Open AccessReview Adaptative Techniques to Reduce Power in Digital Circuits
J. Low Power Electron. Appl. 2011, 1(2), 261-276; doi:10.3390/jlpea1020261
Received: 23 November 2010 / Revised: 13 June 2011 / Accepted: 21 June 2011 / Published: 4 July 2011
Cited by 1 | PDF Full-text (598 KB) | HTML Full-text | XML Full-text
Abstract
CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite [...] Read more.
CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing. Full article
(This article belongs to the Special Issue Selected Topics in Low Power Design - From Circuits to Applications)

Other

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Open AccessTechnical Note Quartz Resonator Based, 0.12 μW, 32768 Hz Oscillator with ±100 ppm Frequency Accuracy
J. Low Power Electron. Appl. 2011, 1(2), 327-333; doi:10.3390/jlpea1020327
Received: 8 August 2011 / Revised: 14 September 2011 / Accepted: 18 September 2011 / Published: 20 September 2011
PDF Full-text (3262 KB) | HTML Full-text | XML Full-text
Abstract
A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system [...] Read more.
A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system clock in low-power, battery-powered and energy harvesting systems. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)

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