Adaptative Techniques to Reduce Power in Digital Circuits
AbstractCMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing.
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Amrutur, B.; Mehta, N.; Dwivedi, S.; Gupte, A. Adaptative Techniques to Reduce Power in Digital Circuits. J. Low Power Electron. Appl. 2011, 1, 261-276.
Amrutur B, Mehta N, Dwivedi S, Gupte A. Adaptative Techniques to Reduce Power in Digital Circuits. Journal of Low Power Electronics and Applications. 2011; 1(2):261-276.Chicago/Turabian Style
Amrutur, Bharadwaj; Mehta, Nandish; Dwivedi, Satyam; Gupte, Ajit. 2011. "Adaptative Techniques to Reduce Power in Digital Circuits." J. Low Power Electron. Appl. 1, no. 2: 261-276.