Special Issue "Selected Topics in Low Power Design - From Circuits to Applications"
Quicklinks
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (15 November 2010)
Special Issue Editor
Editor-in-Chief
Prof. Dr. Alexander Fish
Faculty of Engineering, Bar-Ilan University, Ramat-Gan, 52900, Israel
E-Mail: alexander.fish@biu.ac.il
Phone: +972-3-5317733
Interests: low power electronics; ultra low power VLSI circuits and systems; sub/near-threshold digital logic; low power memory arrays; low power CMOS image sensors; sub-threshold asynchronous design; low power applications; analog and digital on-chip image processing
Special Issue Information
The issue on "Selected Topics in Low Power Design - From Circuits to Applications" will collect a couple of invited articles in celebration of the launching of this new open access journal.
Submission
Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. Papers will be published continuously (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.
Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are refereed through a peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed Open Access quarterly journal published by MDPI.
Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 300 CHF (Swiss Francs).
English correction and/or formatting fees of 250 CHF (Swiss Francs) will be charged in certain cases for those articles accepted for publication that require extensive additional formatting and/or English corrections.
Published Papers (13 papers)
|
Received: 23 November 2010; in revised form: 18 January 2011 / Accepted: 21 January 2011 / Published: 25 January 2011
Show/Hide Abstract
| Download PDF Full-text (208 KB) | Download XML Full-text
Abstract: Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.
|
|
Received: 19 November 2010; in revised form: 14 January 2011 / Accepted: 22 January 2011 / Published: 28 January 2011
Show/Hide Abstract
| Download PDF Full-text (279 KB) | Download XML Full-text | 
Abstract: Ultra low power circuits require robust and reliable operation despite the unavoidable use of low currents and the weak inversion transistor operation region. For analogue domain filtering doubly terminated LC ladder based filter topologies are thus highly desirable as they have very low sensitivities to component values: non-exact component values have a minimal effect on the realised transfer function. However, not all transfer functions are suitable for implementation via a LC ladder prototype, and even when the transfer function is suitable the synthesis procedure is not trivial. The modern circuit designer can thus benefit from an updated treatment of this synthesis procedure. This paper presents a methodology for the design of doubly terminated LC ladder structures making use of the symbolic maths engines in programs such as MATLAB and MAPLE. The methodology is explained through the detailed synthesis of an example 7th order bandpass filter transfer function for use in electroencephalogram (EEG) analysis.
 |
|
Received: 13 December 2010; in revised form: 1 March 2011 / Accepted: 2 March 2011 / Published: 9 March 2011
Show/Hide Abstract
| Download PDF Full-text (9860 KB) | Download XML Full-text
Abstract: In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks—one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplication operation enabling up to 80% savings in terms of silicon area and power compared to oblique based-DT while achieving 91.36% classification accuracy without throughput degradation. The circuit was designed in 0.18 μm Charter CMOS process and tested using a data set acquired with in-house fabricated tin-oxide gas sensors.
|
|
Received: 14 December 2010; in revised form: 4 March 2011 / Accepted: 11 March 2011 / Published: 14 March 2011
Show/Hide Abstract
| Download PDF Full-text (647 KB) | Download XML Full-text
Abstract: A variety of solutions for widening the dynamic range (DR) of CMOS image sensors have been proposed throughout the years. These solutions can be categorized into different groups according to the principle used for DR widening. One of the methods, which is based on autonomous control over the integration time, was implemented by our group. We proposed the multiple resets algorithm, which was successfully implemented in three generations of WDR image sensors. While achieving the same goal of widening the DR of the sensor, each of the implemented imagers had a different architecture, and therefore presented different performance and power figures. This paper reviews designs of the aforementioned sensors and presents a comprehensive analysis of their power consumption. Power-performance tradeoffs are also discussed. Advantages and disadvantages of each sensor are presented.
|
|
Received: 7 December 2010; in revised form: 14 March 2011 / Accepted: 21 March 2011 / Published: 28 March 2011
Show/Hide Abstract
| Download PDF Full-text (882 KB) | Download XML Full-text |
Abstract: In digital pixel sensors (DPS), memory elements typically occupy large silicon area of the pixel, which significantly reduces the pixel’s fill factor while increases its size, power and cost. In this work, we propose to reduce DPS memory’s area and power overhead by reducing the memory requirements with a multi-reset integration scheme, and meanwhile employing a dynamic memory instead of traditionally exploited large 6T-SRAM cell. The operation of the DPS takes advantage from the chronological change of the code, which results in reduced memory needs without affecting the light resolution. In the proposed implementation, a 4-bit in-pixel memory is used to reduce the pixel size, and an 8-bit resolution is achieved with multi-reset scheme. In addition, full complementary metal-oxide-semiconductor (CMOS) 2T DRAM and selective refresh scheme are adoptedto implement the memory elements and further increase the area savings. This paper presents the proposed multi-reset integration methodology and its implementation with dedicated memory circuits. Proposed architecture is validated by a prototype chip fabricated using AMS 0.35 μm CMOS technology. Reported experimental results are compared with relative works.
 |
|
Received: 25 November 2010; in revised form: 18 March 2011 / Accepted: 1 April 2011 / Published: 6 April 2011
Show/Hide Abstract
| Download PDF Full-text (583 KB) | Download XML Full-text
Abstract: Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.
|
|
Received: 24 November 2010; in revised form: 21 March 2011 / Accepted: 7 April 2011 / Published: 11 April 2011
Show/Hide Abstract
| Download PDF Full-text (1539 KB) | Download XML Full-text
Abstract: This paper describes the hardware requirements and design constraints that derive from unique features of body sensor networks (BSNs). Based on the BSN requirements, we examine the tradeoff between custom hardware and commercial off the shelf (COTS) designs for BSNs. The broad range of BSN applications includes situations where either custom chips or COTS design is optimal. For both types of nodes, we survey key techniques to improve energy efficiency in BSNs and identify general approaches to energy efficiency in this space.
|
|
Received: 25 November 2010; in revised form: 11 April 2011 / Accepted: 13 April 2011 / Published: 15 April 2011
Show/Hide Abstract
| Download PDF Full-text (315 KB) | Download XML Full-text
Abstract: A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current.
|
|
Received: 25 November 2010; in revised form: 13 April 2011 / Accepted: 20 April 2011 / Published: 26 April 2011
Show/Hide Abstract
| Download PDF Full-text (3385 KB) | Download XML Full-text
Abstract: Intelligent biomedical devices implies systems that are able to detect specific physiological processes in patients so that particular responses can be generated. This closed-loop capability can have enormous clinical value when we consider the unprecedented modalities that are beginning to emerge for sensing and stimulating patient physiology. Both delivering therapy (e.g., deep-brain stimulation, vagus nerve stimulation, etc.) and treating impairments (e.g., neural prosthesis) requires computational devices that can make clinically relevant inferences, especially using minimally-intrusive patient signals. The key to such devices is algorithms that are based on data-driven signal modeling as well as hardware structures that are specialized to these. This paper discusses the primary application-domain challenges that must be overcome and analyzes the most promising methods for this that are emerging. We then look at how these methods are being incorporated in ultra-low-energy computational platforms and systems. The case study for this is a seizure-detection SoC that includes instrumentation and computation blocks in support of a system that exploits patient-specific modeling to achieve accurate performance for chronic detection. The SoC samples each EEG channel at a rate of 600 Hz and performs processing to derive signal features on every two second epoch, consuming 9 μJ/epoch/channel. Signal feature extraction reduces the data rate by a factor of over 40×, permitting wireless communication from the patient’s head while reducing the total power on the head by 14×.
|
|
Received: 10 November 2010; in revised form: 11 April 2011 / Accepted: 14 April 2011 / Published: 12 May 2011
Show/Hide Abstract
| Download PDF Full-text (1917 KB) | Download XML Full-text
Abstract: Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for implantable devices, with specific focus on developing efficacious but computationally efficient algorithms to detect seizures. Common seizure detection features used to construct algorithms are evaluated and algorithmic, mathematical as well as circuit-level design techniques are suggested to effectively translate the algorithms into hardware implementations on low-power platforms.
|
|
Received: 25 November 2010; in revised form: 2 May 2011 / Accepted: 3 May 2011 / Published: 16 May 2011
Show/Hide Abstract
| Download PDF Full-text (2610 KB) | Download XML Full-text
Abstract: As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.
|
|
Received: 14 December 2010; in revised form: 8 April 2011 / Accepted: 30 April 2011 / Published: 19 May 2011
Show/Hide Abstract
| Download PDF Full-text (963 KB) | Download XML Full-text
Abstract: Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.
|
|
Received: 23 November 2010; in revised form: 13 June 2011 / Accepted: 21 June 2011 / Published: 4 July 2011
Show/Hide Abstract
| Download PDF Full-text (598 KB) | Download XML Full-text
Abstract: CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing.
|
Last update: 4 October 2012
