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Energy Efficient Supply Boosted Comparator Design
AbstractThis paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.
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Ay, S.U. Energy Efficient Supply Boosted Comparator Design. J. Low Power Electron. Appl. 2011, 1, 247-260.View more citation formats
Ay SU. Energy Efficient Supply Boosted Comparator Design. Journal of Low Power Electronics and Applications. 2011; 1(2):247-260.Chicago/Turabian Style
Ay, Suat U. 2011. "Energy Efficient Supply Boosted Comparator Design." J. Low Power Electron. Appl. 1, no. 2: 247-260.