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J. Low Power Electron. Appl. 2011, 1(2), 247-260; doi:10.3390/jlpea1020247

Energy Efficient Supply Boosted Comparator Design

Department of Electrical and Computer Engineering, University of Idaho, Moscow, ID 83844, USA
Received: 6 April 2011 / Revised: 13 June 2011 / Accepted: 20 June 2011 / Published: 24 June 2011
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
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This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.
Keywords: supply boosting; mixed-signal design; low-voltage design; comparator supply boosting; mixed-signal design; low-voltage design; comparator
This is an open access article distributed under the Creative Commons Attribution License (CC BY) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Ay, S.U. Energy Efficient Supply Boosted Comparator Design. J. Low Power Electron. Appl. 2011, 1, 247-260.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert