Special Issue "Industrial Aspects of Low Power Design Recent Trends and Methods"

Quicklinks

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 August 2011)

Special Issue Editors

Guest Editor
Dr. Arkadiy Morgenshtein

Core CAD Technologies Group, Intel Corporation, Haifa 31015, Israel
Guest Editor
Dr. Israel A. Wagner

Circuit Technologies Group, IBM Haifa Research Lab, MATAM, Haifa 31905, Israel
Guest Editor
Prof. Dr. Yakov Roizin

Emerging Technologies,Tower Jazz, Migdal HaEmek 32105, Israel

Special Issue Information

Dear Colleagues,

The Journal of Low Power Electronics and Applications (JLPEA) is seeking original contributions for the forthcoming issue on Industrial Aspects of Low Power Design Recent Trends and Methods. This issue is scheduled for publication in September, 2011. The aim of this issue is to present recent advances and trends of low power methodologies and applications in industry.

Dr. Arkadiy Morgenshtein
Dr. Israel A. Wagner
Prof. Dr. Yakov Roizin
Guest Editors

Keywords

  • fabrication process advances for low power
  • emerging technologies and devices for low power
  • low power circuits and systems design
  • energy efficient processors and DSPs
  • verification for low power
  • EDA tools for power optimization and estimation, recent advances in CAD low-power methodologies
  • low power memories and arrays
  • low power algorithms and architectures
  • applications - case studies of specific low power applications, power-saving enabling solutions

Published Papers (5 papers)

View options order results:
result details:
Displaying articles 1-5
Export citation of selected articles as:

Research

Jump to: Review, Other

Open AccessArticle Multi-Functional Micro Projection Device as Screen Substitute for Low Power Consumption Computing
J. Low Power Electron. Appl. 2012, 2(1), 79-97; doi:10.3390/jlpea2010079
Received: 20 December 2011 / Revised: 20 February 2012 / Accepted: 21 February 2012 / Published: 5 March 2012
PDF Full-text (5588 KB) | HTML Full-text | XML Full-text
Abstract
One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in [...] Read more.
One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the development of low power consumption computing systems. In this paper we present one possible solution involving micro projection device based upon lasers and a digital light processing (DLP) matrix which is a matrix of electrically controllable mirrors capable of translating electrical signal to a time varying projected image. It can serve to substitute a screen and consume ten times less power than a conventional screen. The described device is a multifunctional highly efficient customized DLP light engine being capable of serving as an image projector and simultaneously to support range and topography estimation measurements. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Open AccessArticle Short-Circuit Power Reduction by Using High-Threshold Transistors
J. Low Power Electron. Appl. 2012, 2(1), 69-78; doi:10.3390/jlpea2010069
Received: 15 October 2011 / Revised: 13 February 2012 / Accepted: 21 February 2012 / Published: 1 March 2012
Cited by 3 | PDF Full-text (573 KB) | HTML Full-text | XML Full-text
Abstract
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic [...] Read more.
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic power (PSC/Pdyn) while changing the design process. The analysis shows that the PSC/Pdyn ratio can increase significantly if the VT/Vdd ratio in new process decreases. An analytical expression is also derived for estimation of potential SC power reduction in MTCMOS processes by replacing low-VT transistors by high-VT devices in the same process. The proposed technique allows significant reduction of SC power without the need for process shift. The simulation results show good correlation with the analytical estimation at cell level, while demonstrating an average SC power saving of 36%. The performance impact is also validated, showing that timing degradation is minor and controllable. The proposed optimization technique is applicable to any multi-threshold process. The technique is simple for implementation, and can be easily integrated in the existing optimization tools. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Open AccessArticle Low Power Testing—What Can Commercial Design-for-Test Tools Provide?
J. Low Power Electron. Appl. 2011, 1(3), 357-372; doi:10.3390/jlpea1030357
Received: 16 August 2011 / Revised: 2 December 2011 / Accepted: 5 December 2011 / Published: 9 December 2011
PDF Full-text (251 KB) | HTML Full-text | XML Full-text
Abstract
Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to [...] Read more.
Minimizing power consumption during functional operation and during manufacturing tests has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial design-for-test (DFT) tools’ point of view, this paper describes how DFT tools can help to achieve comprehensive testing of low power designs and reduce test power consumption during test application. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Figures

Review

Jump to: Research, Other

Open AccessReview CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
J. Low Power Electron. Appl. 2012, 2(1), 1-29; doi:10.3390/jlpea2010001
Received: 12 December 2011 / Revised: 14 January 2012 / Accepted: 16 January 2012 / Published: 27 January 2012
Cited by 10 | PDF Full-text (2808 KB) | HTML Full-text | XML Full-text
Abstract
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration [...] Read more.
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)

Other

Jump to: Research, Review

Open AccessTechnical Note Quartz Resonator Based, 0.12 μW, 32768 Hz Oscillator with ±100 ppm Frequency Accuracy
J. Low Power Electron. Appl. 2011, 1(2), 327-333; doi:10.3390/jlpea1020327
Received: 8 August 2011 / Revised: 14 September 2011 / Accepted: 18 September 2011 / Published: 20 September 2011
PDF Full-text (3262 KB) | HTML Full-text | XML Full-text
Abstract
A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system [...] Read more.
A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clock) or main system clock in low-power, battery-powered and energy harvesting systems. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)

Journal Contact

MDPI AG
JLPEA Editorial Office
St. Alban-Anlage 66, 4052 Basel, Switzerland
jlpea@mdpi.com
Tel. +41 61 683 77 34
Fax: +41 61 302 89 18
Editorial Board
Contact Details Submit to JLPEA
Back to Top