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Journal of Low Power Electronics and Applications, Volume 1, Issue 2

2011 September - 5 articles

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Articles (5)

  • Technical Note
  • Open Access
5 Citations
7,745 Views
7 Pages

A 0.12 μW power dissipation quartz oscillator with 32,768 Hz frequency was designed and fabricated. Stability of the oscillator versus power supply and temperature variations was measured. The design is suitable for the role of the RTC (real-time clo...

(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
  • Article
  • Open Access
4 Citations
7,588 Views
24 Pages

The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP) technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassi...

(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
  • Article
  • Open Access
25 Citations
13,219 Views
26 Pages

Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit...

(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
  • Review
  • Open Access
12 Citations
12,120 Views
16 Pages

Adaptative Techniques to Reduce Power in Digital Circuits

  • Bharadwaj Amrutur,
  • Nandish Mehta,
  • Satyam Dwivedi and
  • Ajit Gupte

CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign....

(This article belongs to the Special Issue Selected Topics in Low Power Design - From Circuits to Applications)
  • Article
  • Open Access
5 Citations
7,833 Views
14 Pages

This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The se...

(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
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J. Low Power Electron. Appl. - ISSN 2079-9268