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Abridging the CMOS Technology II

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A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: 20 May 2024 | Viewed by 14177

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Prof. Dr. Hei Wong

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Guest Editor

Department of Electrical Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong, China
Interests: CMOS integrated circuits; high-k dielectric thin films; nanoelectronics; semiconductor device models; MOSFET; approximation theory; ballistic transport; circuit optimisation; electrostatics; elemental semiconductors; field effect transistors; nanowires; numerical analysis; sensitivity; silicon; surface potential; surface roughness; silicon compounds; dielectric thin films; tunnelling; interface states; X-ray photoelectron spectra; electron traps; hafnium compounds, SPICE
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Dear Colleagues,

From either a physics device, fabrication technology, or process economics point of view, the downsizing of silicon-based CMOS devices will soon end. Although new, revolutionary materials and new technologies for the advancement of further integrated electronics are already being researched, due to the development of nanoscale-sized devices, as well as the giga-scale in integration density, complexity in fabrication technology, and the widespread application of the present CMOS technology, which is a cumulative outcome resulting from the relentless advancements and innovation over seven decades, the emerging new materials and new devices are unlikely to replace CMOS technology in the short term. A possible scenario is that the existing CMOS technology will still be, at baseline, the mainstream integration technology for decades to come; alongside this, new material discovery and new technology innovation, on the one hand, could serve as technological options for overcoming some of the constraints of CMOS devices and fabrication technology, and, on the other hand, could enrich and enhance the CMOS technology in certain aspects.

This Special Issue is a continuation of the previously successful Special Issue, entitled, “Abridging the CMOS Technology” (https://www.mdpi.com/journal/nanomaterials/special_issues/CMOS_Technology), and hosted by the same Guest Editors. It serves as a forum for multidisciplinary experts to address various aspects of recent advancements in nanomaterials and nanotechnology that could be abridged to further CMOS technology advancements. The format of articles includes full papers, communications, and reviews. Topics include, but are not limited to:

CMOS device characteristic enhancement with nanomaterials;
Nanofabrication;
Silicon, carbon nanotube, and 2D material integration;
Silicon/carbon silicon/2D material interaction and characterization;
Enriching CMOS technology with 2D material-based devices, sensors and transducers;
Nanophotonics–CMOS integration;
Interconnects and heterogeneous 3D integration;
Nanoscale modeling and computation;
CMOS thermal management with nanomaterials.

Prof. Dr. Hei Wong
Guest Editor

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Keywords

CMOS device
2D material-based devices
sensors
transducers
Nanophotonics

Published Papers (10 papers)

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Research

Jump to: Review

12 pages, 3715 KiB

Open AccessEditor’s ChoiceArticle

Terahertz Detection by Asymmetric Dual Grating Gate Bilayer Graphene FETs with Integrated Bowtie Antenna

by E. Abidi, A. Khan, J. A. Delgado-Notario, V. Clericó, J. Calvo-Gallego, T. Taniguchi, K. Watanabe, T. Otsuji, J. E. Velázquez and Y. M. Meziani

Nanomaterials 2024, 14(4), 383; https://doi.org/10.3390/nano14040383 - 19 Feb 2024

Viewed by 1064

Abstract

An asymmetric dual-grating gate bilayer graphene-based field effect transistor (ADGG-GFET) with an integrated bowtie antenna was fabricated and its response as a Terahertz (THz) detector was experimentally investigated. The device was cooled down to 4.5 K, and excited at different frequencies (0.15, 0.3 and 0.6 THz) using a THz solid-state source. The integration of the bowtie antenna allowed to obtain a substantial increase in the photocurrent response (up to 8 nA) of the device at the three studied frequencies as compared to similar transistors lacking the integrated antenna (1 nA). The photocurrent increase was observed for all the studied values of the bias voltage applied to both the top and back gates. Besides the action of the antenna that helps the coupling of THz radiation to the transistor channel, the observed enhancement by nearly one order of magnitude of the photoresponse is also related to the modulation of the hole and electron concentration profiles inside the transistor channel by the bias voltages imposed to the top and back gates. The creation of local n and p regions leads to the formation of homojuctions (

n p

p n

p p^{+}

) along the channel that strongly affects the overall photoresponse of the detector. Additionally, the bias of both back and top gates could induce an opening of the gap of the bilayer graphene channel that would also contribute to the photocurrent. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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12 pages, 3946 KiB

Open AccessArticle

Magnetically Compatible Brain Electrode Arrays Based on Single-Walled Carbon Nanotubes for Long-Term Implantation

by Jie Xia, Fan Zhang, Luxi Zhang, Zhen Cao, Shurong Dong, Shaomin Zhang, Jikui Luo and Guodong Zhou

Nanomaterials 2024, 14(3), 240; https://doi.org/10.3390/nano14030240 - 23 Jan 2024

Viewed by 889

Abstract

Advancements in brain–machine interfaces and neurological treatments urgently require the development of improved brain electrodes applied for long-term implantation, where traditional and polymer options face challenges like size, tissue damage, and signal quality. Carbon nanotubes are emerging as a promising alternative, combining excellent electronic properties and biocompatibility, which ensure better neuron coupling and stable signal acquisition. In this study, a new flexible brain electrode array based on 99.99% purity of single-walled carbon nanotubes (SWCNTs) was developed, which has 30 um × 40 um size, about 5.1 kΩ impedance, and 14.01 dB signal-to-noise ratio (SNR). The long-term implantation experiment in vivo in mice shows the proposed brain electrode can maintain stable LFP signal acquisition over 12 weeks while still achieving an SNR of 3.52 dB. The histological analysis results show that SWCNT-based brain electrodes induced minimal tissue damage and showed significantly reduced glial cell responses compared to platinum wire electrodes. Long-term stability comes from SWCNT’s biocompatibility and chemical inertness, the electrode’s flexible and fine structure. Furthermore, the new brain electrode array can function effectively during 7-Tesla magnetic resonance imaging, enabling the collection of local field potential and even epileptic discharges during the magnetic scan. This study provides a comprehensive study of carbon nanotubes as invasive brain electrodes, providing a new path to address the challenge of long-term brain electrode implantation. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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10 pages, 1574 KiB

Open AccessArticle

Nature of the Metal Insulator Transition in High-Mobility 2D_Si-MOSFETs

by F. Elmourabit, S. Dlimi, A. El Moutaouakil, F. Id Ouissaaden, A. Khoukh, L. Limouny, H. Elkhatat and A. El Kaaouachi

Nanomaterials 2023, 13(14), 2047; https://doi.org/10.3390/nano13142047 - 11 Jul 2023

Cited by 1 | Viewed by 824

Abstract

Our investigation focuses on the analysis of the conductive properties of high-mobility 2D-Si-MOSFETs as they approach the critical carrier density,

n_{s c}

(approximately

0.72 \times 10^{11} {c m}^{- 2}

), which marks the metal insulator transition (MIT). In close [...] Read more.

Our investigation focuses on the analysis of the conductive properties of high-mobility 2D-Si-MOSFETs as they approach the critical carrier density,

n_{s c}

(approximately

0.72 \times 10^{11} {c m}^{- 2}

), which marks the metal insulator transition (MIT). In close proximity to the

n_{s c}

, the conductivity exhibits a linear dependence on the temperature (T). By examining the extrapolated conductivity at the absolute zero temperature (T = 0), denoted as

σ_{0}

, as a function of the electron density

n_{s}

, we identify two distinct regimes with varying

σ_{0} (n_{s})

patterns, indicating the existence of two different phases. The transition from one of these two regimes to another, coinciding with

n_{s c}

, is abrupt and serves as the focus of our investigation. Our aim is to establish the possibility of a percolation type transition in the 2D-Si-MOSFETs’ sample. In fact, we observed that the model of percolation is applicable only for densities very close to

n_{s c}^{*} = n_{2}

(where

n_{2}

is the linear extrapolation of

σ_{0}

), indicating the percolation type transition essentially represents a phase transition at the zero temperature. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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10 pages, 7853 KiB

Open AccessArticle

A Coupling Mechanism between Flicker Noise and Hot Carrier Degradations in FinFETs

by Minghao Liu, Zixuan Sun, Haoran Lu, Cong Shen, Lining Zhang, Runsheng Wang and Ru Huang

Nanomaterials 2023, 13(9), 1507; https://doi.org/10.3390/nano13091507 - 28 Apr 2023

Viewed by 1298

Abstract

A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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10 pages, 2159 KiB

Open AccessArticle

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature

by Daoqin Wang, Zongjin Jiang, Linhan Li, Deliang Zhu, Chunfeng Wang, Shun Han, Ming Fang, Xinke Liu, Wenjun Liu, Peijiang Cao and Youming Lu

Nanomaterials 2023, 13(8), 1422; https://doi.org/10.3390/nano13081422 - 20 Apr 2023

Cited by 3 | Viewed by 1483

Abstract

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device’s performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices’ performance. ZnO:H/ZnO-TFT has the best overall performance when H₂/(Ar + H₂) = 0.13% with a mobility of 12.10 cm²/Vs, an on/off current ratio of 2.32 × 10⁷, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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14 pages, 3008 KiB

Open AccessArticle

A Simulation of the Effect of External and Internal Parameters on the Synthesis of a Carbyne with More than 6000 Atoms for Emerging Continuously Tunable Energy Barriers in CNT-Based Transistors

by Chi Ho Wong, Yan Ming Yeung, Xin Zhao, Wing Cheung Law, Chak Yin Tang, Chee Leung Mak, Chi Wah Leung, Lei Shi and Rolf Lortz

Nanomaterials 2023, 13(6), 1048; https://doi.org/10.3390/nano13061048 - 14 Mar 2023

Viewed by 1469

Abstract

Transistors made up of carbon nanotube CNT have demonstrated excellent current–voltage characteristics which outperform some high-grade silicon-based transistors. A continuously tunable energy barrier across semiconductor interfaces is desired to make the CNT-based transistors more robust. Despite that the direct band gap of the carbyne inside a CNT can be widely tuned by strain, the size of the carbyne cannot be controlled easily. The production of a monoatomic chain with more than 6000 carbon atoms is an enormous technological challenge. To predict the optimal chain length of a carbyne in different molecular environments, we have developed a Monte Carlo model in which a finite-length carbyne with a size of 4000–15,000 atoms is encapsulated by a CNT at finite temperatures. Our simulation shows that the stability of the carbyne@nanotube is strongly influenced by the nature and porosity of the CNT, the external pressure, the temperature, and the chain length. We have observed an initiation of the chain-breaking process in a compressed carbyne@nanotube. Our work provides much-needed input for optimizing the carbyne length to produce carbon chains much longer than 6000 atoms at ~300 K. Design rules are proposed for synthesizing ~1% strained carbyne@(6,5)CNT as a component in CNT-based transistors to tune the energy barriers continuously. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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11 pages, 2412 KiB

Open AccessArticle

Poole–Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor

by Hei Wong and Kuniyuki Kakushima

Nanomaterials 2023, 13(3), 411; https://doi.org/10.3390/nano13030411 - 19 Jan 2023

Cited by 2 | Viewed by 1588

Abstract

This work reports, for the first time, the phenomenon of lateral Poole–Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current–voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole–Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole–Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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Review

Jump to: Research

36 pages, 10668 KiB

Open AccessReview

Contacts at the Nanoscale and for Nanomaterials

by Hei Wong, Jieqiong Zhang and Jun Liu

Nanomaterials 2024, 14(4), 386; https://doi.org/10.3390/nano14040386 - 19 Feb 2024

Cited by 1 | Viewed by 1370

Abstract

Contact scaling is a major challenge in nano complementary metal–oxide–semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current–voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts’ characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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21 pages, 6344 KiB

Open AccessReview

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO₂/Al₂O₃ Nanolaminated Stacks

by Dencho Spassov and Albena Paskaleva

Nanomaterials 2023, 13(17), 2456; https://doi.org/10.3390/nano13172456 - 30 Aug 2023

Cited by 2 | Viewed by 1874

Abstract

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO₂/Al₂O₃-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO₂ is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO₂/Al₂O₃-based stacks. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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16 pages, 8177 KiB

Open AccessReview

Graphene-Based ESD Protection for Future ICs

by Cheng Li, Zijin Pan, Weiquan Hao, Xunyu Li, Runyu Miao and Albert Wang

Nanomaterials 2023, 13(8), 1426; https://doi.org/10.3390/nano13081426 - 20 Apr 2023

Viewed by 1621

Abstract

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection. Full article

(This article belongs to the Special Issue Abridging the CMOS Technology II)

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