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JLPEA
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Ultra-low Power Embedded Systems
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Ultra-low Power Embedded Systems

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 December 2018) | Viewed by 16768

Special Issue Editors

Prof. Dr. William Fornaciari

E-Mail Website
Guest Editor
Politecnico di Milano – DEIB, Milano, Italy
Interests: embedded systems; high-performance computing; energy aware design of Hw and Sw; multi-many cores; performance predictability and real-time; cybersecurity
Special Issues, Collections and Topics in MDPI journals
Dr. Davide Zoni

E-Mail Website
Guest Editor
Politecnico di Milano, Department of Electronics, Information and Bioengineering, 20133 Milan, Italy
Interests: low-power embedded multi-cores; coherence protocols; on-chip interconnect and hardware-level side-channel countermeasures
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The future of the computing continuum is linking low-end embedded systems with the entire Hw/Sw stack, encompassing also high-performance systems. Many possible solutions to the issue of power consumption can be shared across these abstraction layers. Embedded systems play a key role to the spread of intelligence in everyday applications and one of the critical success factor is to reduce the power and energy consumption, dramatically. Such goal can be achieved by tackling the problem from different angles, including the design of the hardware, software, sensing and communication components, as well as by considering in a vertical way the development of the application, as for example required for the next generation of IoT solutions. Smart, run-time adaptable and ultra low power edge devices are the only viable option that can meet these demands.

Within the above scenario, this special issue focuses on the latest developments in the field of designing ultra low power embedded systems. The call reflects a broad range of research topics: from theoretical aspects down to best practices and experiments with existing and novel platforms and applications. Authors are invited to submit regular papers following the JLPEA (Journal of Low Power Electronics and Applications) submission guidelines within the remit of this special issue call.

Topics include but are not limited to:

  • Micro-architectural solutions for the monitoring, control and optimization of the power consumption of computing modules
  • Energy harvesting and storage approaches in conjunction with low energy/low power processing for embedded applications
  • Ultra-low power IoT Technologies and Embedded Systems Architectures
  • End-to end solutions to reduce power consumption, including techniques targeting communication costs and edge computation.
  • Run-time management of resources and workloads for multi-many cores and heterogeneous architectures
  • Application-aware design and optimization of hardware and software of embedded ultra low power processors and of possible accelerators
  • Specific VLSI, CAD, and microarchitecture techniques for ultra low power embedded systems, including management of sensors
  • Wearables, Body Sensor Networks, Smart Portable Devices including studies on new device technologies applied to ultra low power systems
  • Application of approximate computing to the problem of reducing the power consumption

Prof. William Fornaciari
Dr. Davide Zoni
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (2 papers)

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19 pages, 98081 KiB  
Article
Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
by Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Mikel Azkarate-Askasua, Peio Onaindia, Tomaso Poggi, Nera González Romero, Elena Quesada Gonzalez, Timmy Sundström, Salvador Peiró Frasquet, Patricia Balbastre, Tage Mohammadat, Johnny Öberg, Yosab Bebawy, Roman Obermaisser, Adele Maleki, Alina Lenz and Duncan Graham
J. Low Power Electron. Appl. 2019, 9(1), 12; https://doi.org/10.3390/jlpea9010012 - 11 Mar 2019
Cited by 2 | Viewed by 7323
Abstract
With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway [...] Read more.
With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication. Full article
(This article belongs to the Special Issue Ultra-low Power Embedded Systems)
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19 pages, 755 KiB  
Article
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era
by Giovanni Scotti and Davide Zoni
J. Low Power Electron. Appl. 2019, 9(1), 9; https://doi.org/10.3390/jlpea9010009 - 19 Feb 2019
Cited by 11 | Viewed by 8762
Abstract
The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the [...] Read more.
The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks. Full article
(This article belongs to the Special Issue Ultra-low Power Embedded Systems)
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