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CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
TowerJazz Corporation, Migdal Ha’Emek, 10556, Israel
The Department of Materials Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel
Received: 12 December 2011; in revised form: 14 January 2012 / Accepted: 16 January 2012 / Published: 27 January 2012
Abstract: Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed.
Keywords: low leakage; low power; layout optimization; transistor scaling; leakage-related-stressors; design-aware leakage reduction
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Cite This Article
MDPI and ACS Style
Shauly, E.N. CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations. J. Low Power Electron. Appl. 2012, 2, 1-29.
Shauly EN. CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations. Journal of Low Power Electronics and Applications. 2012; 2(1):1-29.
Shauly, Eitan N. 2012. "CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations." J. Low Power Electron. Appl. 2, no. 1: 1-29.