Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
4.5
2.7
Journals
Applied Sciences
Special Issues
Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies
share announcement

Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Energy Science and Technology".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 15515

Special Issue Editors

Prof. Dr. Alfio Dario Grasso

E-Mail Website
Guest Editor
Department of Electrical, Electronics and Computer Engineering (DIEEI), University of Catania, 95125 Catania CT, Italy
Interests: electronic engineering; microelectronics; electronic systems; analog integrated circuits; ultra-low-voltage integrated circuits; energy harvesting; low-power CMOS design
Dr. Andrea Ballo

E-Mail Website
Guest Editor
Department of Electrical, Electronics and Computer Engineering (DIEEI), University of Catania, 95125 Catania, CT, Italy
Interests: electronic engineering; switched capacitor AC/DC–DC converters; energy harvesting; low-power CMOS design; microelectronics
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The down scaling of CMOS technology has enabled the implementation of complex analog and digital functions on the same die. This has come with a progressive reduction of the supply voltage below 1 V to reduce the electric field within MOS devices. Even lower supply voltage may be requested for ultra-low-power systems, such as biomedical implantable/wearable electronic devices and energy-autonomous Internet of Things (IoT) nodes.

In this context, the design of integrated electronic systems represents a challenging task, especially for analog circuits, since the designer is asked to develop novel techniques and topologies to get a good level of performance while maintaining robustness and reliability in low-voltage low-power conditions.

The aim of this Special Issue is to attract researchers in the area of integrated circuits to highlight the recent advances in low-voltage design techniques. Both review articles, describing the state-of-the-art, and original research articles are welcome.

The topics to be covered in this Special Issue include, but are not limited to, the following:

  • Conventional and nonconventional low-voltage analog and digital design techniques
  • Theory, design, and new applications of sub-1-V analog and digital circuits
  • Circuits for IoT nodes and implantable/wearable biomedical devices
  • Low-voltage power-efficient analog-to-digital converters
  • Circuits and systems for energy harvesting
  • Power management of sub-1-V integrated digital and analog systems
  • Time-based analog signal processing

Prof. Dr. Alfio Dario Grasso
Dr. Andrea Ballo
Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Low-voltage analog and digital design techniques
  • Low-power low-voltage analog front-end (AFE) circuits
  • Circuits for implantable and wearable devices
  • Energy harvesting
  • Circuits for Internet of Things
  • Switched capacitor DC-DC converters
  • Subthreshold analog and digital circuits
  • Near threshold computing
  • Bulk-driven amplifiers
  • Inverter-based amplifiers
  • Ring amplifiers
  • Digitally assisted analog circuits
  • Multistage amplifiers

Published Papers (4 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

Jump to: Review

13 pages, 3543 KiB  
Article
Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies
by Egidio Ragonese
Appl. Sci. 2022, 12(4), 2103; https://doi.org/10.3390/app12042103 - 17 Feb 2022
Cited by 2 | Viewed by 2753
Abstract
This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components [...] Read more.
This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs. Full article
(This article belongs to the Special Issue Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies)
►▼ Show Figures

Figure 1

19 pages, 4751 KiB  
Article
Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques
by Antonio Lopez-Martin, Maria Pilar Garde, Jose M. Algueta-Miguel, Javier Beloso-Legarra, Ramon G. Carvajal and Jaime Ramirez-Angulo
Appl. Sci. 2021, 11(7), 3271; https://doi.org/10.3390/app11073271 - 6 Apr 2021
Cited by 4 | Viewed by 3849
Abstract
Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, [...] Read more.
Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance. Full article
(This article belongs to the Special Issue Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies)
►▼ Show Figures

Figure 1

16 pages, 481 KiB  
Article
A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier
by Francesco Centurelli, Riccardo Della Sala, Giuseppe Scotti and Alessandro Trifiletti
Appl. Sci. 2021, 11(6), 2528; https://doi.org/10.3390/app11062528 - 11 Mar 2021
Cited by 23 | Viewed by 2876
Abstract
A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. [...] Read more.
A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations. Full article
(This article belongs to the Special Issue Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies)
►▼ Show Figures

Figure 1

Review

Jump to: Research

21 pages, 3621 KiB  
Review
A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices
by Andrea Ballo, Michele Bottaro and Alfio Dario Grasso
Appl. Sci. 2021, 11(6), 2487; https://doi.org/10.3390/app11062487 - 10 Mar 2021
Cited by 32 | Viewed by 5109
Abstract
This paper aims to review the recent architectures of power management units for ultrasound-based energy harvesting, while focusing on battery-less implantable medical devices. In such systems, energy sustainability is based on piezoelectric devices and a power management circuit, which represents a key building [...] Read more.
This paper aims to review the recent architectures of power management units for ultrasound-based energy harvesting, while focusing on battery-less implantable medical devices. In such systems, energy sustainability is based on piezoelectric devices and a power management circuit, which represents a key building block since it maximizes the power extracted from the piezoelectric devices and delivers it to the other building blocks of the implanted device. Since the power budget is strongly constrained by the dimension of the piezoelectric energy harvester, complexity of topologies have been increased bit by bit in order to achieve improved power efficiency also in difficult operative conditions. With this in mind, the introduced work consists of a comprehensive presentation of the main blocks of a generic power management unit for ultrasound-based energy harvesting and its operative principles, a review of the prior art and a comparative study of the performance achieved by the considered solutions. Finally, design guidelines are provided, allowing the designer to choose the best topology according to the given design specifications and technology adopted. Full article
(This article belongs to the Special Issue Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-4
Back to TopTop