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J. Low Power Electron. Appl., Volume 8, Issue 3 (September 2018)

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Open AccessArticle Waxberry-Like Nanosphere Li4Mn5O12 as High Performance Electrode Materials for Supercapacitors
J. Low Power Electron. Appl. 2018, 8(3), 32; https://doi.org/10.3390/jlpea8030032
Received: 13 June 2018 / Revised: 27 August 2018 / Accepted: 4 September 2018 / Published: 11 September 2018
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Abstract
Porous materials have superior electrochemical performance owing to its their structure, which could increase the specific and contact area with the electrode. The spinel Li4Mn5O12 has a three-dimensional tunnel structure for a better diffusion path, which has the
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Porous materials have superior electrochemical performance owing to its their structure, which could increase the specific and contact area with the electrode. The spinel Li4Mn5O12 has a three-dimensional tunnel structure for a better diffusion path, which has the advantage of lithium ion insertion and extraction in the framework. However, multi-space spherical materials with single morphologies are rarely studied. In this work, waxberry-like and raspberry-like nanospheres for Li4Mn5O12 have been fabricated by the wet chemistry and solid-state methods for the first time. The diameter of a single waxberry- and raspberry-like nanosphere is about 1 μm and 600 nm, respectively. The specific capacitance of Li4Mn5O12 was 535 mF cm−2 and 147.25 F g−1 at the scan rate of 2 mV s−1, and the energy density was 110.7 Wh kg−1, remaining at 70% after 5000th charge-discharge cycles. Compared with raspberry-like nanosphere Li4Mn5O12, the waxberry-like nanoporous spinel Li4Mn5O12 shows the better electrochemical performance and stability; furthermore, these electrochemical performances have been improved greatly compared to the previous studies. All these results indicate that the waxberry-like nanoporous spinel Li4Mn5O12 could provide a potential application in high performance supercapacitors. Full article
(This article belongs to the Special Issue Flexible Electronics and Self-Powered Systems)
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Open AccessArticle Clock Topologies for Molecular Quantum-Dot Cellular Automata
J. Low Power Electron. Appl. 2018, 8(3), 31; https://doi.org/10.3390/jlpea8030031
Received: 29 June 2018 / Revised: 15 August 2018 / Accepted: 18 August 2018 / Published: 8 September 2018
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Abstract
Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few
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Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few mobile charges. Device switching occurs through quantum mechanical inter-dot charge tunneling, and devices are interconnected via the electrostatic field. QCA devices are implemented using arrays of QCA cells. A molecular implementation of QCA may support THz-scale clocking or better at room temperature. Molecular QCA may be clocked using an applied electric field, known as a clocking field. A time-varying clocking field may be established using an array of conductors. The clocking field determines the flow of data and calculations. Various arrangements of clocking conductors are laid out, and the resulting electric field is simulated. It is shown that that control of molecular QCA can enable feedback loops, memories, planar circuit crossings, and versatile circuit grids that support feedback and memory, as well as data flow in any of the ordinal grid directions. Logic, interconnect and memory now become indistinguishable, and the von Neumann bottleneck is avoided. Full article
(This article belongs to the Special Issue Quantum-Dot Cellular Automata (QCA) and Low Power Application)
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Open AccessArticle Exponentially Adiabatic Switching in Quantum-Dot Cellular Automata
J. Low Power Electron. Appl. 2018, 8(3), 30; https://doi.org/10.3390/jlpea8030030
Received: 15 August 2018 / Revised: 5 September 2018 / Accepted: 5 September 2018 / Published: 7 September 2018
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Abstract
We calculate the excess energy transferred into two-dot and three-dot quantum dot cellular automata systems during switching events. This is the energy that must eventually be dissipated as heat. The adiabaticity of a switching event is quantified using the adiabaticity parameter of Landau
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We calculate the excess energy transferred into two-dot and three-dot quantum dot cellular automata systems during switching events. This is the energy that must eventually be dissipated as heat. The adiabaticity of a switching event is quantified using the adiabaticity parameter of Landau and Zener. For the logically reversible operations of WRITE or ERASE WITH COPY, the excess energy transferred to the system decreases exponentially with increasing adiabaticity. For the logically irreversible operation of ERASE WITHOUT COPY, considerable energy is transferred and so must be dissipated, in accordance with the Landauer Principle. The exponential decrease in energy dissipation with adiabaticity (e.g., switching time) distinguishes adiabatic quantum switching from the usual linear improvement in classical systems. Full article
(This article belongs to the Special Issue Quantum-Dot Cellular Automata (QCA) and Low Power Application)
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Open AccessArticle An Improved Proposed Single Phase Transformerless Inverter with Leakage Current Elimination and Reactive Power Capability for PV Systems Application
J. Low Power Electron. Appl. 2018, 8(3), 29; https://doi.org/10.3390/jlpea8030029
Received: 16 July 2018 / Revised: 22 August 2018 / Accepted: 25 August 2018 / Published: 6 September 2018
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Abstract
Single-phase transformerless inverters are broadly studied in literature for residential-scale PV applications due to their great advantages in reducing system weight, cost and elevating system efficiency. The design of transformerless inverters is based on the galvanic isolation method to eliminate the generation of
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Single-phase transformerless inverters are broadly studied in literature for residential-scale PV applications due to their great advantages in reducing system weight, cost and elevating system efficiency. The design of transformerless inverters is based on the galvanic isolation method to eliminate the generation of leakage current. Unfortunately, the use of the galvanic isolation method alone cannot achieve constant common mode voltage (CMV). Therefore, a complete elimination of leakage current cannot be achieved. In addition, modulation techniques of single-phase transformerless inverters are designed for the application of the unity power factor. Indeed, next-generation PV systems are required to support reactive power to enable connectivity to the utility grid. In this paper, a proposed single-phase transformerless inverter is modified with the clamping method to achieve constant CMV during all inverter operating modes. Furthermore, the modulation technique is modified by creating a new current path in the negative power region. As a result, a bidirectional current path is created in the negative power region to achieve reactive power generation. The simulation results show that the CMV is completely clamped at half the DC link voltage and the leakage current is almost completely eliminated. Furthermore, a reactive power generation is achieved with the modified modulation techniques. Additionally, the total harmonic distortion (THD) of the grid current with the conventional and a modified modulation technique is analyzed. The efficiency of the system is enhanced by using wide-bandgap (WBG) switching devices such as SiC MOSFET. It is observed that the efficiency of the system decreased with reactive power generation due to the bidirectional current path, which leads to increasing conduction losses. Full article
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Open AccessArticle Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors
J. Low Power Electron. Appl. 2018, 8(3), 28; https://doi.org/10.3390/jlpea8030028
Received: 16 June 2018 / Revised: 18 August 2018 / Accepted: 21 August 2018 / Published: 24 August 2018
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Abstract
Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM
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Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis
J. Low Power Electron. Appl. 2018, 8(3), 27; https://doi.org/10.3390/jlpea8030027
Received: 16 June 2018 / Revised: 2 August 2018 / Accepted: 13 August 2018 / Published: 17 August 2018
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Abstract
This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of
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This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle Energy Efficiency Due to a Common Global Timebase—Synchronizing FlexRay to 802.1AS Networks as a Foundation
J. Low Power Electron. Appl. 2018, 8(3), 26; https://doi.org/10.3390/jlpea8030026
Received: 12 July 2018 / Revised: 31 July 2018 / Accepted: 9 August 2018 / Published: 17 August 2018
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Abstract
Modern automotive control applications require a holistic time-sensitive development. Nowadays, this is achieved by technologies specifically designed for the automotive domain, like FlexRay, which offer a fault-tolerant time synchronization mechanism built into the protocol. Currently, the automotive industry adopts the Ethernet within the
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Modern automotive control applications require a holistic time-sensitive development. Nowadays, this is achieved by technologies specifically designed for the automotive domain, like FlexRay, which offer a fault-tolerant time synchronization mechanism built into the protocol. Currently, the automotive industry adopts the Ethernet within the car, not only for embedding consumer electronics, but also as a fast and reliable backbone for control applications. Still, low-cost but highly reliable sensors connected over the traditional Controller Area Network (CAN) deliver data needed for autonomous driving. To fusion the data efficiently among all, a common timebase is required. The alternative would be oversampling, which uses more time and energy, e.g., at least double the perception rates of sensors. Ethernet and CAN do require the latter by default. Hence, a global synchronization mechanism eases tremendously the design of a low power automotive network and is the foundation of a transparent global clock. In this article, we present the first step: Synchronizing legacy FlexRay networks to the upcoming Ethernet backbone, which will contain a precise clock over the generalized Precision Time Protocol (gPTP) defined in IEEE 802.1AS. FlexRay then could still drive its strengths with deterministic transmission behavior and possibly also serve as a redundant technology for fail-operational system design. Full article
(This article belongs to the Special Issue Automotive Low Power Technologies)
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Open AccessArticle Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis
J. Low Power Electron. Appl. 2018, 8(3), 25; https://doi.org/10.3390/jlpea8030025
Received: 15 June 2018 / Revised: 21 July 2018 / Accepted: 27 July 2018 / Published: 30 July 2018
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Abstract
In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a
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In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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Open AccessArticle Effectiveness of Molecules for Quantum Cellular Automata as Computing Devices
J. Low Power Electron. Appl. 2018, 8(3), 24; https://doi.org/10.3390/jlpea8030024
Received: 29 June 2018 / Revised: 23 July 2018 / Accepted: 26 July 2018 / Published: 28 July 2018
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Abstract
Notwithstanding the increasing interest in Molecular Quantum-Dot Cellular Automata (MQCA) as emerging devices for computation, a characterization of their behavior from an electronic standpoint is not well-stated. Devices are typically analyzed with quantum physics-based approaches which are far from the electronic engineering world
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Notwithstanding the increasing interest in Molecular Quantum-Dot Cellular Automata (MQCA) as emerging devices for computation, a characterization of their behavior from an electronic standpoint is not well-stated. Devices are typically analyzed with quantum physics-based approaches which are far from the electronic engineering world and make it difficult to design, simulate and fabricate molecular devices. In this work, we define new figures of merits to characterize the molecules, which are based on the post-processing of results obtained from ab initio simulations. We define the Aggregated Charge (AC), the electric-field generated at the receiver molecule (EFGR), the Vin–Vout and Vin–AC transcharacteristics (VVT and VACT), the Vout maps (VOM) and the MQCA cell working zones (CWZ). These quantities are compatible with an electronic engineering point of view and can be used to analyze the capability of molecules to propagate information. We apply and verify the methodology to three molecules already proposed in the literature for MQCA and we state to which extent these molecules can be effective for computation. The adopted methodology provides the quantitative characterization of the molecules necessary for digital designers, to design digital circuits, and for technologists, to the future fabrication of MQCA devices. Full article
(This article belongs to the Special Issue Quantum-Dot Cellular Automata (QCA) and Low Power Application)
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Open AccessArticle Efficient 3D-TLM Modeling and Simulation for the Thermal Management of Microwave AlGaN/GaN HEMT Used in High Power Amplifiers SSPA
J. Low Power Electron. Appl. 2018, 8(3), 23; https://doi.org/10.3390/jlpea8030023
Received: 27 April 2018 / Revised: 12 June 2018 / Accepted: 20 June 2018 / Published: 23 June 2018
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Abstract
A three-dimensional thermal simulation investigation for the thermal management of GaN-on-SiC monolithic microwave integrated circuits (MMICs) of consisting multi-fingers (HEMTs) is presented. The purpose of this work is to demonstrate the utility and efficiency of the three-dimensional Transmission Line Matrix method (3D-TLM) in
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A three-dimensional thermal simulation investigation for the thermal management of GaN-on-SiC monolithic microwave integrated circuits (MMICs) of consisting multi-fingers (HEMTs) is presented. The purpose of this work is to demonstrate the utility and efficiency of the three-dimensional Transmission Line Matrix method (3D-TLM) in a thermal analysis of high power AlGaN/GaN heterostructures single gate and multi-fingers HEMT SSPA (solid state power amplifiers). The self-heating effects induce thermal cross-talk between individual fingers in multi-finger AlGaN/GaN that affect device performance and reliability. Gate-finger temperature differences only arise after a transient state, due to the beginning of thermal crosstalk which is attributed to the finite rate of heat diffusion between gate fingers. The TLM method accounts for the real geometrical structure and the non-linear thermal conductivities of GaN and SiC in order to improve the realistic calculations accuracy heat dissipation and thermal behavior of the device. In addition, two types of heat sources located on the top of GaN layer are considered in thermal simulations: Nano-scale hotspot as a pulsed wave heat source under gate and micro-scale hotspot as a continuous wave heat source, between gate and drain. Heat diffusion however, occurs not only between individual gate fingers (inter-finger) in a multi-finger HEMT, but also within each gate finger (intra-finger). To compare results, a Micro-Raman Spectroscopy experience is conducted to obtain a detailed and accurate temperature distribution. Good agreement between the microscopic spectral measurement and TLM simulation results is observed by accepting an error less than 2.2% relative to a maximum temperature. Results show that the 3D-TLM method is suitable for understanding heat management in particular for microwave devices AlGaN/GaN HEMTs SSPA amplifier. TLM method helps to select and locates the expected hot spots and to highlight the need of thermal study pre-design in order to minimize the system-level thermal dissipation and lead therefore to higher reliability. Full article
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Open AccessArticle A Survey of Low Voltage and Low Power Amplifier Topologies
J. Low Power Electron. Appl. 2018, 8(3), 22; https://doi.org/10.3390/jlpea8030022
Received: 3 May 2018 / Revised: 11 June 2018 / Accepted: 20 June 2018 / Published: 23 June 2018
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Abstract
Reducing voltage supply is one of the most effective way to reduce the power consumption, but, on the other hand it is a challenging choice for the analog designers. In this paper, different topologies, well-suited for low voltage and ultra-low voltage supply, are
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Reducing voltage supply is one of the most effective way to reduce the power consumption, but, on the other hand it is a challenging choice for the analog designers. In this paper, different topologies, well-suited for low voltage and ultra-low voltage supply, are depicted, investigated, designed in the same standard 180 nm technology and compared, highlighting the benefits and the possible applications. Full article
(This article belongs to the Special Issue CMOS Low Power Design)
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