Previous Article in Journal
Effectiveness of Molecules for Quantum Cellular Automata as Computing Devices
Previous Article in Special Issue
A Survey of Low Voltage and Low Power Amplifier Topologies
Article Menu

Export Article

Open AccessArticle
J. Low Power Electron. Appl. 2018, 8(3), 25; https://doi.org/10.3390/jlpea8030025

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

1
Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA
2
Fermi National Accelerator Laboratory, Batavia, IL 60510, USA
*
Author to whom correspondence should be addressed.
Received: 15 June 2018 / Revised: 21 July 2018 / Accepted: 27 July 2018 / Published: 30 July 2018
(This article belongs to the Special Issue CMOS Low Power Design)
View Full-Text   |   Download PDF [6864 KB, uploaded 31 July 2018]   |  

Abstract

In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis. View Full-Text
Keywords: Content Addressable Memory (CAM); TCAM; multi-Vdd; multi supply; associative memory; tunable operation; standby power; searchline power; matchline power Content Addressable Memory (CAM); TCAM; multi-Vdd; multi supply; associative memory; tunable operation; standby power; searchline power; matchline power
Figures

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).
SciFeed

Share & Cite This Article

MDPI and ACS Style

Joshi, S.; Li, D.; Ogrenci-Memik, S.; Deptuch, G.; Hoff, J.; Jindariani, S.; Liu, T.; Olsen, J.; Tran, N. Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis. J. Low Power Electron. Appl. 2018, 8, 25.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top