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J. Low Power Electron. Appl. 2014, 4(3), 214-230; doi:10.3390/jlpea4030214

Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

1
HGST Inc., 3403 Yerba Buena Road, San Jose, CA 95135, USA
2
LIRMM - UMR CNRS 5506 - University of Montpellier 2, 161 Rue Ada, Montpellier 34095, France
*
Authors to whom correspondence should be addressed.
Received: 18 October 2013 / Revised: 9 March 2014 / Accepted: 20 March 2014 / Published: 28 August 2014
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
View Full-Text   |   Download PDF [2961 KB, uploaded 28 August 2014]   |  

Abstract

Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC. View Full-Text
Keywords: semiconductors; VLSI; SoC; memory; non-volatile memory (NVM); Magnetic random access memory (MRAM); embedded systems; memory hierarchy semiconductors; VLSI; SoC; memory; non-volatile memory (NVM); Magnetic random access memory (MRAM); embedded systems; memory hierarchy
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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MDPI and ACS Style

Cargnini, L.V.; Torres, L.; Brum, R.M.; Senni, S.; Sassatelli, G. Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory. J. Low Power Electron. Appl. 2014, 4, 214-230.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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