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J. Low Power Electron. Appl. 2014, 4(3), 231-251; doi:10.3390/jlpea4030231

The Impact of Process Scaling on Scratchpad Memory Energy Savings

Department of Electrical & Computer Engineering, University of Utah, 1692 Warnock Engineering Bldg., 72 S. Central Campus Dr., Salt Lake City, UT 84112, USA
Division of Biology and Biological Engineering, California Institute of Technology, Mail Code 216-76, 1200 E, California Blvd., Pasadena, CA 91125, USA
Charleston Rd, Palo Alto, CA 94303, USA
The manuscript is an extended version of a conference paper titled “Scratchpad Memories in the Context of Process Scaling”, which was presented at the 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).
Author to whom correspondence should be addressed.
Received: 11 June 2014 / Revised: 22 August 2014 / Accepted: 1 September 2014 / Published: 9 September 2014
View Full-Text   |   Download PDF [630 KB, uploaded 9 September 2014]   |  


Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory. Increases in leakage as a percentage of total power particularly impact applications that rarely access memory. This study examines how the benefits of scratchpad memories have changed in newer processes, based on the measured performance of the WIMS (Wireless Integrated MicroSystems) microcontroller implemented in 180- and 65-nm processes and upon simulations of this microcontroller implemented in a 32-nm process. The results demonstrate that scratchpad memories will continue to improve the power dissipation of many applications, given the leakage anticipated in the foreseeable future. View Full-Text
Keywords: scratchpad memory; loop cache; process scaling; low power; microprocessor; computer architecture; embedded scratchpad memory; loop cache; process scaling; low power; microprocessor; computer architecture; embedded

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This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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MDPI and ACS Style

Redd, B.; Kellis, S.; Gaskin, N.; Brown, R. The Impact of Process Scaling on Scratchpad Memory Energy Savings. J. Low Power Electron. Appl. 2014, 4, 231-251.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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